# US 10,319,437 B2 · Apparatus and method for identifying memory cells for data refresh based on monitor cell in a resistive memory device

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- Number: US 10,319,437 B2
- Document ID: US10319437B2
- Status: Granted
- Kind: B2
- Application number: 15/710,247
- Filed: 2017-09-20
- Published: 2019-03-21
- Granted: 2019-06-11
- Earliest claimed: 2017-09-20
- Assignees: SanDisk Technologies LLC
- Applicants: SanDisk Technologies LLC
- Inventors: Juan Saenz; Christopher J Petti
- Web page: https://patentgrep.com/patent/US10319437B2

## CPC

- G11C 13/0002: {using resistive RAM [RRAM] elements}
- G11C 13/0023: {Address circuits or decoders}
- G11C 13/0033: {Disturbance prevention or evaluation; Refreshing of disturbed memory data}
- G11C 13/0061: {Timing circuits or methods}
- G11C 13/0069: {Writing or programming circuits or methods}
- G11C 2013/0073: {Write using bi-directional cell biasing}
- G11C 2213/71: Three dimensional array
- G11C 2213/75: Array having a NAND structure comprising, for example, memory cells in series or memory elements in series, a memory element being a memory cell in parallel with an access transistor
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

Technology is described for identifying non-volatile memory cells having data that should be refreshed. The technology could be used to identify which groups of memory cells that store cold data should have a data refresh. In one aspect, a non-volatile storage device has at least one monitor memory cell associated with a group of data memory cells. The non-volatile storage device may use different programming techniques to program the data and monitor memory cells. In one aspect, the programming technique used for the monitor memory cell is less stable with respect to state than the technique used to program the associated data memory cells. The state of the monitor memory cell may change in a predictable manner, such that the state of the monitor cell may be sensed periodically to determine whether the associated data memory cells should be refreshed.

## Claims

### Claim 1

An apparatus, comprising:
a plurality of non-volatile memory cells comprising a group of data memory cells and a monitor memory cell, wherein the plurality of non-volatile memory cells are resistive random access memory (ReRAM) cells; and
a control circuit in communication with the plurality of non-volatile memory cells, the control circuit configured to:
program the group of data memory cells with a first programming technique, including program the group of data memory cells to their program resistance from a first resistance direction;
program the monitor memory cell with a second programming technique for which state retention is less stable than the first programming technique, including program the monitor memory cell to its monitor resistance from a second resistance direction opposite the first resistance direction, the monitor memory cell programmed contemporaneously with the group of data memory cells; and
identify the group of data memory cells for data refresh responsive to a determination that the monitor memory cell has incurred a state shift of more than a threshold.

### Claim 2 (depends on 1)

The apparatus of claim 1, wherein the second programming technique creates a resistance in the monitor memory cell that is less stable than the resistance in ones of the group of data memory cells.

### Claim 3 (depends on 1)

The apparatus of claim 1, wherein:
to program the group of data memory cells with the first programming technique from the first resistance direction the control circuit is further configured to program the group of data memory cells to a program resistance from a lower resistance; and
to program the monitor memory cell with the second programming technique from the second resistance direction the control circuit is further configured to program the monitor memory cell to a monitor resistance from a higher resistance.

### Claim 4 (depends on 1)

The apparatus of claim 1, wherein:
to program the group of data memory cells with the first programming technique from the first resistance direction the control circuit is further configured to program the group of data memory cells to a program resistance from a higher resistance; and
to program the monitor memory cell with the second programming technique from the second resistance direction the control circuit is further configured to program the monitor memory cell to a monitor resistance from a lower resistance.

### Claim 5 (depends on 1)

The apparatus of claim 1, wherein the group of data memory cells and the monitor memory cell are barrier modulated cells (BMC) resistive random access memory cells.

### Claim 6 (depends on 1)

The apparatus of claim 1, wherein the state shift of more than the threshold is a resistance of the monitor memory cell changing by more than an allowed amount.

### Claim 7 (depends on 1)

The apparatus of claim 1, wherein the control circuit is further configured to:
sense a plurality of monitor memory cells in parallel, wherein each of the monitor memory cells is associated with a group of data memory cells that were programmed using the first programming technique when the associated monitor memory cell was programmed using the second programming technique; and
identify ones of the groups of data memory cells for data refresh based on which of the plurality of monitor memory cells incurred a state shift of more than the threshold.

### Claim 8 (depends on 1)

The apparatus of claim 1, further comprising a memory die, wherein the plurality of non-volatile memory cells and the control circuit reside on the memory die.

### Claim 9 (depends on 8)

The apparatus of claim 8, wherein the control circuit is further configured to send a message from the memory die to a memory controller that identifies the group of data memory cells for data refresh.

### Claim 10 (depends on 1)

The apparatus of claim 1, wherein the control circuit is further configured to:
refresh data in the group of data memory cells responsive to identifying the group of data memory cells.

### Claim 11 (depends on 1)

The apparatus of claim 1, wherein the control circuit is further configured to:
apply a sense voltage to the monitor memory cell after programming the monitor memory cell with the second programming technique;
sense a current of the monitor memory cell in response to the sense voltage; and
determine whether the monitor memory cell has incurred the state shift of more than the threshold based on a magnitude of the current.

### Claim 12

A method of operating a memory system having a plurality of resistive random access memory (ReRAM) cells, wherein the plurality of ReRAM cells are barrier modulated cells (BMC), the method comprising:
programming a group of data barrier modulated cells with a first programming technique to program resistances;
programming a monitor barrier modulated cell with a second programming technique to a monitor resistance contemporaneously with programming the group of data barrier modulated cells, the second programming technique creating a monitor resistance in the monitor barrier modulated cell that is less stable than the program resistances in ones of the group of data barrier modulated cells; and
refreshing data in the group of data barrier modulated cells responsive to a determination that the monitor barrier modulated cell has incurred a resistance change of more than a threshold.

### Claim 13 (depends on 12)

The method of claim 12, wherein:
programming the group of data barrier modulated cells with the first programming technique comprises programming the group of data barrier modulated cells to the program resistances from a lower resistance; and
programming the monitor barrier modulated cell with the second programming technique comprises programming the monitor barrier modulated cell to the monitor resistance from a higher resistance.

### Claim 14 (depends on 12)

The method of claim 12, wherein:
programming the group of data barrier modulated cells with the first programming technique comprises programming the group of data barrier modulated cells to the program resistances from a higher resistance; and
programming the monitor barrier modulated cell with the second programming technique comprises programming the monitor barrier modulated cell to the monitor resistance from a lower resistance.

### Claim 15 (depends on 12)

The method of claim 12, further comprising sensing a plurality of monitor barrier modulated cells in parallel, wherein each of the monitor barrier modulated cells is associated with a group of data barrier modulated cells that were programmed using the first programming technique when the associated monitor barrier modulated cell was programmed using the second programming technique; and
identifying ones of the groups of data barrier modulated cells for data refresh based on which of the plurality of monitor barrier modulated cells incurred a state shift of more than the threshold.

### Claim 16

A non-volatile memory system, comprising:
a plurality of resistive random access memory (ReRAM) cells, wherein the plurality of ReRAM cells are barrier modulated memory cells comprising a non-volatile memory material having a semiconductor material layer adjacent a conductive oxide material layer, including a group of data barrier modulated memory cells and a monitor barrier modulated memory cell;
data memory cell programming means for programming the group of data barrier modulated memory cells with a first programming technique;
monitor memory cell programming means for programming the monitor barrier modulated memory cell with a second programming technique at about the same time as the group of data barrier modulated memory cells are programmed, the monitor memory cell programming means further for creating a monitor resistance in the monitor barrier modulated memory cell that is less stable than a program resistance in ones of the group of data barrier modulated memory cells;
sensing means for determining whether the monitor resistance of the monitor barrier modulated memory cell has changed by more than a threshold; and
data refresh means for refreshing data in the group of data barrier modulated memory cells responsive to a determination that the monitor resistance has changed by more than the threshold.

### Claim 17 (depends on 16)

The non-volatile memory system of claim 16, wherein:
the data memory cell programming means is further for programming the group of data barrier modulated memory cells to their respective program resistances from a first resistance direction; and
the monitor memory cell programming means is further for programming the monitor barrier modulated memory cell to the monitor resistance from a second resistance direction opposite the first resistance direction.

### Claim 18

An apparatus, comprising:
a plurality of resistive random access memory cells comprising a group of data barrier modulated memory cells (BMC) and a monitor barrier modulated memory cell; and
a control circuit in communication with the plurality of resistive random access memory cells, the control circuit configured to:
program the group of data barrier modulated memory cells with a first programming technique;
program the monitor barrier modulated memory cell with a second programming technique for which state retention is less stable than the first programming technique, the monitor barrier modulated memory cell programmed contemporaneously with the group of data barrier modulated memory cells; and
identify the group of data barrier modulated memory cells for data refresh responsive to a determination that the monitor barrier modulated memory cell has incurred a state shift of more than a threshold.

### Claim 19

An apparatus, comprising:
a memory array comprising a plurality of groups of data non-volatile memory cells;
the memory array further comprising a plurality of monitor non-volatile memory cells; and
a control circuit in communication with the plurality of groups of data non-volatile memory cells and the plurality of monitor non-volatile memory cells, the control circuit configured to:
program the plurality of groups of data non-volatile memory cells with a first programming technique;
program the plurality of monitor non-volatile memory cells with a second programming technique for which state retention is less stable than the first programming technique, wherein each of the monitor memory cells is associated with a group of data memory cells that were programmed using the first programming technique when the associated monitor memory cell was programmed using the second programming technique, each monitor non-volatile memory cell programmed contemporaneously with one of the groups of data non-volatile memory cells;
sense the plurality of monitor non-volatile memory cells in parallel; and
in response to at least one of the monitor non-volatile memory cells incurring a state shift of more than a threshold, identify the group or groups of data non-volatile memory cells that are associated with the at least one monitor non-volatile memory cell incurring a state shift of more than the threshold for data refresh.

### Claim 20

An apparatus, comprising:
a memory die comprising a plurality of non-volatile memory cells and a control circuit;
the plurality of non-volatile memory cells comprising a group of data memory cells and a monitor memory cell; and
the control circuit in communication with the plurality of non-volatile memory cells, the control circuit configured to:
program the group of data memory cells with a first programming technique, including program the group of data memory cells to their program resistance from a lower resistance;
program the monitor memory cell with a second programming technique for which state retention is less stable than the first programming technique, including program the monitor memory cell to its monitor resistance from a higher resistance, the monitor memory cell programmed contemporaneously with the group of data memory cells;
identify the group of data memory cells for data refresh responsive to a determination that the monitor memory cell has incurred a state shift of more than a threshold; and
send a message from the memory die to a memory controller that identifies the group of data memory cells for data refresh.