# US 10,319,435 B2 · Write assist for a memory device and methods of forming the same

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- Number: US 10,319,435 B2
- Document ID: US10319435B2
- Status: Granted
- Kind: B2
- Application number: 16/021,172
- Filed: 2018-06-28
- Published: 2019-02-28
- Granted: 2019-06-11
- Earliest claimed: 2017-08-30
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company Limited
- Inventors: Sahil Preet Singh; Yen-Huei Chen; Hung-Jen Liao
- Web page: https://patentgrep.com/patent/US10319435B2

## CPC

- G11C 11/419: Read-write [R-W] circuits
- G11C 5/147: {Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops (G11C5/141 takes precedence)}
- G11C 5/148: {Details of power up or power down circuits, standby circuits or recovery circuits}
- G11C 7/1009: {Data masking during input/output}
- G11C 7/12: Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
- G11C 11/4097: Bit-line organisation, e.g. bit-line layout, folded bit lines
- G11C 11/412: using field-effect transistors only
- G11C 11/413: Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 86/215: {comprising FinFETs}
- H10D 89/10: Integrated device layouts
- H10B 10/12: {comprising a MOSFET load element}
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

A semiconductor memory device includes an array of memory cells arranged in a plurality of rows and columns, with each memory cell including a plurality of bit cell transistors. The semiconductor memory device further includes a plurality of write assist circuits, including one or more write assist circuits within each column of the array of memory cells, each write assist circuit configured to provide a core voltage to memory cells within the same column and to reduce the core voltage during a write operation. The array of memory cells and the plurality of write assist circuits have a common semiconductor layout.

## Claims

### Claim 1

A semiconductor memory device, comprising:
an array of memory cells arranged in a plurality of rows and columns, each memory cell including a plurality of bit cell transistors; and
a plurality of write assist circuits, including one or more write assist circuits within each column of the array of memory cells, each write assist circuit configured to provide a core voltage to memory cells within the same column and to reduce the core voltage during a write operation,
the array of memory cells and the plurality of write assist circuits having a common semiconductor layout that includes a repeating pattern of gate regions and active regions, wherein each of the plurality of write assist circuits utilizes a layout footprint of the common semiconductor layout that is equivalent to a footprint for three adjacent memory cells within a column of the array of memory cells.

### Claim 2 (depends on 1)

The semiconductor memory device of claim 1, wherein the plurality of write assist circuits each include four PMOS transistors fabricated using four PMOS regions in three rows of the layout footprint, wherein one of the four PMOS transistors is fabricated in a top row, two of the four PMOS transistors are fabricated in a middle row, and another one of the four PMOS transistors is fabricated in a bottom row.

### Claim 3 (depends on 1)

The semiconductor memory device of claim 1, wherein the plurality of bit cell transistors and the plurality of write assist circuits are each fabricated using common design rules for static random access memory (SRAM) transistors.

### Claim 4 (depends on 1)

The semiconductor memory device of claim 1, wherein the plurality of write assist circuits are disposed adjacent to the array of memory cells such that there is no buffer area between the array of memory cells and the plurality of write assist circuits.

### Claim 5 (depends on 1)

The semiconductor memory device of claim 1, wherein a common fin structure is shared across the one or more write assist circuits and bit cell transistors within each column of the array of memory cells.

### Claim 6 (depends on 1)

The semiconductor device of claim 1, wherein the plurality of write assist circuits each include,
a first pair of transistors coupled between a pull-up voltage and the a core voltage bus, and
a second pair of transistors coupled between a pull-down voltage and the core voltage bus, the second pair of transistors each having a gate terminal that receives an enable signal that causes the second pair of transistors to connect the core voltage bus to the pull-down voltage during write operations.

### Claim 7 (depends on 6)

The semiconductor device of claim 6, wherein the first pair of transistors each include a gate terminal that receives a shut-down signal, the shut-down signal causing the first pair of transistors to disconnect the core voltage bus from the pull-up voltage during a shut-down operation.

### Claim 8 (depends on 1)

The semiconductor device of claim 1, wherein the plurality of write assist circuits are controlled by an enable signal that is coupled to the one or more write assist circuits within a particular column during the write operation by a multiplexer.

### Claim 9 (depends on 1)

The semiconductor device of claim 1, wherein the plurality of write assist circuits are controlled by an enable signal that is coupled to each column of the array of memory cells through a masking circuit that is configured to mask the enable signal from the column except during write operations.

### Claim 10

A write assist circuit for a semiconductor memory device, comprising:
a core voltage bus configured to provide power to memory cells within the semiconductor memory device;
a first pair of transistors coupled between a pull-up voltage and the core voltage bus;
a second pair of transistors coupled between a pull-down voltage and the core voltage bus, the second pair of transistors each having a gate terminal that receives an enable signal that causes the second pair of transistors to connect the core voltage bus to the pull-down voltage during write operations to the memory cells,
the write assist circuit and the memory cells having a common semiconductor layout that includes a repeating pattern of gate regions and active regions, wherein the write assist circuit utilizes a layout footprint of the common semiconductor layout that is equivalent to a footprint for three adjacent memory cells.

### Claim 11 (depends on 10)

The write assist circuit of claim 10, wherein the write assist circuit includes four PMOS transistors fabricated using four PMOS regions in three rows of the layout footprint, wherein one of the four PMOS transistors is fabricated in a top row, two of the four PMOS transistors are fabricated in middle row, and another one of the four PMOS transistors is fabricated in a bottom row.

### Claim 12 (depends on 10)

The write assist circuit of claim 10, wherein the write assist circuit is disposed adjacent to a column of memory cells within the semiconductor memory device such that there is no buffer area between the write assist circuit and the column of memory cells.

### Claim 13 (depends on 10)

The write assist circuit of claim 10, wherein the first and second pair of transistors in the write assist circuit and the memory cells are each fabricated using common design rules for static random access memory (SRAM) transistors.

### Claim 14 (depends on 10)

The write assist circuit of claim 10, wherein a first common fin structure is shared across the first pair of transistors and the memory cells, and a second common fin structure is shared across the second pair of transistors and the memory cells.

### Claim 15 (depends on 10)

The write assist circuit of claim 10, wherein the first pair of transistors each include a gate terminal that receives a shut-down signal, the shut-down signal causing the first pair of transistors to disconnect the core voltage bus from the pull-up voltage during a shut-down operation.

### Claim 16 (depends on 10)

The write assist circuit of claim 10, wherein the core voltage bus is configured to provide power to one column of memory cells within an array of memory cells within the semiconductor memory device.

### Claim 17

A method of controlling a semiconductor memory device that includes an array of memory cells arranged in a plurality of rows and columns and one or more write assist circuits within each column of the array of memory cells, the method comprising:
providing a core voltage to memory cells within a column of the array of memory cells; and
during a write operation, causing the one or more write assist circuits in the column to reduce the core voltage,
wherein the one or more write assist circuits and the memory cells have a common static random access memory (SRAM) semiconductor layout that includes a repeating pattern of gate regions and active regions, and
wherein the each of the one or more write assist circuits utilizes a layout footprint of the common SRAM semiconductor layout that is equivalent to a footprint for three adjacent memory cells with the column of the array of memory cells.

### Claim 18 (depends on 17)

The method of claim 17, wherein the one or more write assist circuits each include four PMOS transistors fabricated using four PMOS regions in three rows of the layout footprint, wherein one of the four PMOS transistors is fabricated in a top row, two of the four PMOS transistors are fabricated in middle row, and another one of the four PMOS transistors is fabricated in a bottom row.

### Claim 19 (depends on 17)

The method of claim 17, wherein a common the one or more write assist circuits and the array of memory cells are each fabricated using common design rules for static random access memory (SRAM) transistors.

### Claim 20 (depends on 17)

The method of claim 17, further comprising,
providing an enable signal that causes the one or more write assist circuits to connect a core voltage bus to a pull-down voltage during the write operation.