# US 10,319,434 B2 · Static random access memory cell capable of performing differential operation

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- Number: US 10,319,434 B2
- Document ID: US10319434B2
- Status: Granted
- Kind: B2
- Application number: 15/962,573
- Filed: 2018-04-25
- Published: 2018-11-01
- Granted: 2019-06-11
- Earliest claimed: 2017-04-26
- Assignees: Industry-Academic Cooperation Foundation, Yonsei University
- Applicants: Industry-Academic Cooperation Foundation, Yonsei University
- Inventors: Seong Ook Jung; Ju Hyun Park; Han Wool Jeong; Tae Woo Oh
- Web page: https://patentgrep.com/patent/US10319434B2

## CPC

- G11C 11/419: Read-write [R-W] circuits
- G11C 7/227: {Timing of memory operations based on dummy memory elements or replica circuits}
- G11C 8/10: Decoders
- G11C 11/412: using field-effect transistors only
- G11C 11/418: Address circuits
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

Disclosed is an SRAM cell capable of performing a differential operation. An SRAM cell according to an embodiment of the present disclosure may include a data node portion including four transistors constituting first and second data nodes; a data controller including first and second pass-gate transistors configured to control read and write of data in the first and second data nodes; and a control transistor connected to the data node portion through the second data node and configured to be controlled based on a driving voltage of a second word line having an opposite polarity to a first word line transmitting a driving voltage to the data controller.

## Claims

### Claim 1

A Static Random Access Memory (SRAM) cell, comprising:
a data node portion comprising four transistors constituting first and second data nodes;
a data controller comprising first and second pass-gate transistors configured to control read and write of data in the first and second data nodes; and
a control transistor connected to the data node portion through the second data node and configured to be controlled based on a driving voltage of a second word line having an opposite polarity to a first word line transmitting a driving voltage to the data controller,
wherein the data node portion comprises first and second pull-up transistors and first and second pull-down transistors,
wherein a drain terminal of the control transistor is connected to a gate terminal of the first pull-up transistor, a gate terminal of the first pull-down transistor, and a source terminal of the second pull-up transistor through the second data node,
a source terminal of the control transistor is connected to a source terminal of the second pass-gate transistor and a drain terminal of the second pull-down transistor through a third data node, and
a gate terminal of the control transistor is connected to the second word line, and
wherein gate terminals of the first and second pass-gate transistors are connected to the first word line,
a drain terminal of the first pass-gate transistor is connected to a first Bit Line (BL), and
a drain terminal of the second pass-gate transistor is connected to a second BL.

### Claim 2 (depends on 1)

The SRAM cell according to claim 1, wherein the first and second BLs are precharged to a voltage corresponding to a positive value before a read operation.

### Claim 3 (depends on 1)

The SRAM cell according to claim 1, further comprising a word line driver configured to transmit a driving voltage corresponding to a negative value to the first word line and transmit a driving voltage corresponding to a positive value to the second word line in an initial state of operation.

### Claim 4 (depends on 3)

The SRAM cell according to claim 3, wherein the word line driver transmits the driving voltage corresponding to the positive value to the first word line and transmits the driving voltage corresponding to the negative value to the second word line, at the start of a read operation.

### Claim 5 (depends on 4)

The SRAM cell according to claim 4, wherein the control transistor receives the driving voltage corresponding to the negative value through the second word line to be turned off at the start of the read operation, and
the first and second pass-gate transistors receive the driving voltage corresponding to the positive value through the first word line to be turned on at the start of the read operation.

### Claim 6 (depends on 5)

The SRAM cell according to claim 5, wherein a charge from the first BL is discharged through the first pass-gate transistor and the first pull-down transistor during a read operation for first data corresponding to a negative value.

### Claim 7 (depends on 6)

The SRAM cell according to claim 6, wherein the charge from the first BL is introduced into the first data node, and discharges a voltage of a third data node by increasing a voltage of the first data node, during the read operation for first data, and
the second data node maintains a voltage of the second data node according to turn-off of the control transistor when the voltage of the first data node increases and, accordingly, the voltage of the third data node is discharged.

### Claim 8 (depends on 7)

The SRAM cell according to claim 7, further comprising a read buffer portion configured to read the first data stored in the first data node using the voltage maintained in the second data node.

### Claim 9 (depends on 8)

The SRAM cell according to claim 8, wherein the read buffer portion reads the second data using the voltage of the second data node maintained based on the turned-off state of the control transistor during a read operation for the second data corresponding to a negative value.

### Claim 10 (depends on 9)

The SRAM cell according to claim 9, wherein a charge from the second BL is discharged through the second pass-gate transistor and the second pull-down transistor.

### Claim 11 (depends on 3)

The SRAM cell according to claim 3, wherein the word line driver transmits the driving voltage corresponding to the positive value to the first word line and transmits the driving voltage corresponding to the negative value to the second word line, at the start of a write operation.

### Claim 12 (depends on 11)

The SRAM cell according to claim 11, wherein the word line driver switches the driving voltage transmitted to the second word line from the negative value to the positive value when at least one of the charge from the first BL and the charge from the second BL is discharged for a predetermined time.

### Claim 13 (depends on 3)

The SRAM cell according to claim 3, further comprising a signal delay processor configured to control write yield delay based on at least one inverter comprised in a write yield delay controller and control read yield delay based on at least one inverter comprised in a read yield delay controller.

### Claim 14 (depends on 13)

The SRAM cell according to claim 13, wherein the signal delay processor shares an inverter delay line with a circuit generating a Sense Amplifier Enable (SAE) signal and a Word Line Enable (WLEN) signal.

### Claim 15

A method of controlling an SRAM cell, the SRAM cell comprising a data node portion comprising four transistors constituting first and second data nodes; a data controller comprising first and second pass-gate transistors configured to control read and write of data in the first and second data nodes; and a control transistor connected to the data node portion through the second data node and configured to be controlled based on a driving voltage of a second word line having an opposite polarity to a first word line transmitting a driving voltage to the data controller,
wherein the data node portion comprises first and second pull-up transistors and first and second pull-down transistors,
wherein a drain terminal of the control transistor is connected to a gate terminal of the first pull-up transistor, a gate terminal of the first pull-down transistor, and a source terminal of the second pull-up transistor through the second data node,
a source terminal of the control transistor is connected to a source terminal of the second pass-gate transistor and a drain terminal of the second pull-down transistor through a third data node, and
a gate terminal of the control transistor is connected to the second word line,
wherein gate terminals of the first and second pass-gate transistors are connected to the first word line,
a drain terminal of the first pass-gate transistor is connected to a first Bit Line (BL),
a drain terminal of the second pass-gate transistor is connected to a second BL, and
wherein a word line driver switches a driving voltage transmitted to the second word line from a negative value to a positive value when at least one of a charge from the first BL and a charge from the second BL is discharged for a predetermined time.