# US 10,319,429 B2 · SRAM with error correction in retention mode

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- Number: US 10,319,429 B2
- Document ID: US10319429B2
- Status: Granted
- Kind: B2
- Application number: 15/982,835
- Filed: 2018-05-17
- Published: 2019-03-07
- Granted: 2019-06-11
- Earliest claimed: 2017-09-06
- Assignees: Ambiq Micro, Inc.
- Applicants: Ambiq Micro, Inc.
- Inventors: Christophe J. Chevallier; Stephen James Sheafor
- Web page: https://patentgrep.com/patent/US10319429B2

## CPC

- G11C 11/4125: {Cells incorporating circuit means for protecting against loss of information}
- G06F 11/1048: {using arrangements adapted for a specific error detection or correction feature}
- G11C 11/5621: {using charge storage in a floating gate}
- G11C 15/043: {using capacitive charge storage elements}
- G11C 15/046: {using non-volatile storage elements}
- G11C 16/3459: {Circuits or methods to verify correct programming of nonvolatile memory cells}
- G11C 29/50: Marginal testing, e.g. race, voltage or current testing
- G11C 29/50016: {of retention}
- G11C 11/419: Read-write [R-W] circuits
- G11C 2029/0411: {Online error correction}
- G11C: STATIC STORES (semiconductor memory devices H10B)
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

A method for storing information in SRAM bit cell arrays provides for lowering voltage supplied to the SRAM bit cell arrays, with voltage lowering controlled by a connected voltage control circuit. Writing, reading, and correcting information storable in the SRAM bit cell arrays is accomplished using an error correcting code (ECC) block connected to at least some of the SRAM bit cell arrays. The ECC block is configurable to repair stored information.

## Claims

### Claim 1

An apparatus comprising:
a SRAM array with an adjustable power supply and peripheral circuitry;
a register connected to peripheral circuitry to store a retention voltage value for the adjustable power supply, wherein the peripheral circuitry has an ECC circuit to detect at least one error in a SRAM word; and
wherein the retention voltage value is set to a level ensuring loss of at least some SRAM bits in SRAM words retained in the SRAM array.

### Claim 2 (depends on 1)

The apparatus of claim 1, further comprising:
a tester programmed to perform (a)-(f) until a proportion of lost bits meets a threshold condition, wherein (a)-(f) comprise:
(a) writing first data to the SRAM array;
(b) reduce voltage to the SRAM array to a current retention voltage;
(c) read second data back from the SRAM array;
(d) determine the proportion of lost bits by evaluating the second data relative to the first data;
(e) if the proportion of lost bits does not meet the threshold condition, reduce the current retention voltage; and
(f) if the proportion of lost bits meets the threshold condition, store a last value for the current retention voltage at which the threshold condition was not met in the register.

### Claim 3 (depends on 2)

The apparatus of claim 2, wherein the threshold condition is more than n out of m bits lost, where n and m are predetermined integers.

### Claim 4 (depends on 3)

The apparatus of claim 3, wherein n is 1 and m is 39.

### Claim 5 (depends on 2)

The apparatus of claim 2, wherein the tester is further configured to disable the ECC circuit when performing (a)-(f).

### Claim 6 (depends on 5)

The apparatus of claim 5, further comprising a sense amplifier configured to read from the SRAM array, an output of the sense amplifier being input to the ECC circuit when not disabled.

### Claim 7 (depends on 2)

The apparatus of claim 2, wherein the tester is further programmed to:
detect multiple errors at a same bit location of the SRAM array;
at (d), exclude lost bits at the same bit location from a calculation of the proportion of lost bits.

### Claim 8 (depends on 2)

The apparatus of claim 2, wherein the tester is further programmed to perform (c) by raising the voltage to the SRAM array to the operational voltage prior to reading the second data back from the SRAM array.

### Claim 9 (depends on 2)

The apparatus of claim 2, wherein the tester is further programmed to perform (b) by waiting for a predetermined period at the current retention voltage.

### Claim 10 (depends on 1)

The apparatus of claim 1, wherein the ECC circuit is further programmed to:
raise voltage to the SRAM array to an operation voltage; and
repair data within the SRAM array according to ECC codes stored in the SRAM array blocks.

### Claim 11

A method comprising:
writing data to a SRAM array, the data including error correction code (ECC) data with the voltage powering the SRAM array being an operation voltage;
lowering the voltage powering the SRAM array to a retention voltage that is lower than the operation voltage and at least some SRAM bits in the SRAM array are lost; and
raising the voltage powering the SRAM array to the operation voltage and repairing the data using the ECC data.

### Claim 12 (depends on 11)

The method of claim 11, further comprising:
reading a value from a retention voltage register; and
lowering the voltage powering the SRAM array to the retention voltage according to the value.

### Claim 13 (depends on 11)

The method of claim 11, further comprising:
performing (a)-(f) until a proportion of lost bits meets a threshold condition, wherein (a)-(f) comprise:
(a) writing first data to the SRAM array;
(b) reducing voltage to the SRAM array to a current retention voltage;
(c) reading second data back from the SRAM array;
(d) determining the proportion of lost bits by evaluating the second data relative to the first data; and
(e) when the proportion of lost bits does not meet the threshold condition, reducing the current retention voltage;
(f) when the proportion of lost bits meets the threshold condition, storing a last value for the current retention voltage at which the threshold condition was not met in the register.

### Claim 14 (depends on 13)

The method of claim 13, wherein the threshold condition is n out of m bits, where n and m are predetermined integers.

### Claim 15 (depends on 14)

The method of claim 14, wherein n is 1 and m is 39.

### Claim 16 (depends on 13)

The method claim 13, further comprising refraining from performing error correction when performing (a)-(f).

### Claim 17 (depends on 13)

The method of claim 13, further comprising performing (a)-(f) upon startup of a device hosting the SRAM array.

### Claim 18 (depends on 13)

The method of claim 13, further comprising:
detecting multiple errors at one or more bit locations of the SRAM array;
at (d), excluding lost bits at the one or more bit locations from a calculation of the proportion of lost bits.

### Claim 19 (depends on 13)

The method of claim 13, further comprising, at (c), raising the voltage to the SRAM array to the operational voltage prior to reading the second data back from the SRAM array.

### Claim 20 (depends on 13)

The method of claim 13, further comprising, at (b), waiting for a predetermined period at the current retention voltage.