# US 10,319,423 B2 · Memory device with a low-current reference circuit

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 10,319,423 B2
- Document ID: US10319423B2
- Status: Granted
- Kind: B2
- Application number: 15/800,700
- Filed: 2017-11-01
- Published: 2018-05-31
- Granted: 2019-06-11
- Earliest claimed: 2016-11-28
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company Limited
- Inventors: Chia-Fu Lee; Hon-Jarn Lin; Yu-Der Chih
- Web page: https://patentgrep.com/patent/US10319423B2

## CPC

- G11C 11/161: {details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell}
- G11C 7/06: Sense amplifiers; Associated circuits {, e.g. timing or triggering circuits}
- G11C 7/062: {Differential amplifiers of non-latching type, e.g. comparators, long-tailed pairs}
- G11C 7/14: Dummy cell management; Sense reference voltage generators
- G11C 11/15: using multiple magnetic layers (G11C11/155 takes precedence)
- G11C 11/1673: {Reading or sensing circuits or methods}
- G11C 11/1675: {Writing or programming circuits or methods}
- H10N 50/80: Constructional details
- G11C 11/165: {Auxiliary circuits}
- G11C 2207/063: Current sense amplifiers
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H10N: ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR

## Abstract

A memory device includes a memory cell unit, a reference circuit, and a sense amplifier. The memory cell unit includes a memory cell. The reference circuit is configured to generate a reference current and includes a plurality of magnetic resistive elements. At least one of the magnetic resistive elements is in a high resistance state. The sense amplifier is coupled to the memory cell unit and the reference circuit and is configured to compare a current that flows through the memory cell to the reference current to sense a bit of data stored in the memory cell, to amplify a level of the sensed bit of data, and to output the amplified bit of data.

## Claims

### Claim 1

A memory device comprising:
a memory cell unit including a memory cell;
a reference circuit configured to generate a reference current and including:
an arrangement of a plurality of resistive elements, at least one of which is a magnetic resistive element in a high resistance state;
at least two transistors coupled to the plurality of resistive elements and coupled to each other;
a metal short between at least two of the plurality of resistive elements and the at least two transistors, the metal short configured to control the generation of the reference current; and
a sense amplifier coupled to the memory cell unit and the reference circuit and configured to compare a current that flows through the memory cell to the reference current to sense a bit of data stored in the memory cell and to output the sensed bit of data.

### Claim 2 (depends on 1)

The memory device of claim 1, wherein the resistive elements are arranged in parallel with each other.

### Claim 3 (depends on 1)

The memory device of claim 1, further comprising a second memory cell unit coupled to the sense amplifier;
wherein the reference circuit provides the reference current to the sense amplifier for the sense amplifier to use when sensing a bit of data stored in the second memory cell unit.

### Claim 4 (depends on 1)

The memory device of claim 1, wherein multiple control transistors of the reference circuit are controlled during initialization to set a desired resistance of the reference circuit;
wherein a single one of the multiple control transistors is operated to generate the reference current.

### Claim 5 (depends on 1)

The memory device of claim 1, wherein the reference current is based on a sum of currents that flow through the plurality of resistive elements.

### Claim 6 (depends on 1)

The memory device of claim 1, wherein the magnetic resistive element in a high resistance state is a magnetic tunnel junctions (MTJ) in an anti-parallel state.

### Claim 7 (depends on 1)

The memory device of claim 1, wherein the reference circuit further includes:
a resistive unit that is coupled to a magnetic resistive element and that has a substantially constant resistance.

### Claim 8 (depends on 7)

The memory device of claim 7, wherein the magnetic resistive element and the resistive unit are coupled in parallel.

### Claim 9 (depends on 1)

The memory device of claim 1, further comprising:
a word line coupled to the memory cell unit for activating the memory cell; and
a reference word line coupled to one transistor of the at least two transistors for activating the reference circuit.

### Claim 10

A memory device comprising:
a memory cell unit including a memory cell;
a sense amplifier coupled to the memory cell unit and configured to compare a current that flows through the memory cell to a reference current to sense a bit of data stored in the memory cell and to output the amplified bit of data; and
a reference circuit coupled to the sense amplifier, configured to generate the reference current, and including
a pair of magnetic resistive elements coupled in parallel and in a high resistance state;
a pair of transistors coupled to the magnetic resistive elements and coupled to each other; and
a metal short between the pair of magnetic resistive elements and the pair of transistors, the metal short configured to control the generation of the reference current through one transistor of the pair of transistors.

### Claim 11 (depends on 10)

The memory device of claim 10, wherein at least one of the magnetic resistive elements is a magnetic tunneling junction (MTJ) in an anti-parallel state.

### Claim 12 (depends on 10)

The memory device of claim 10, further comprising a resistive unit having a substantially constant resistance and coupled in series with the magnetic resistive elements.

### Claim 13 (depends on 10)

The memory device of claim 10, wherein the pair of transistors are selectively controllable so as to control contributions of the magnetic restrictive elements to the reference current.

### Claim 14

A method comprising:
generating a reference current that corresponds to a resistance of a magnetic resistive element that is in a high resistance state, a resistance of a resistive unit that has a substantially constant resistance, and a metal short between the magnetic resistive element and a pair of transistors, the pair of transistors coupled to each other;
comparing a current that flows through a memory cell to the reference current to sense a bit of data stored in the memory cell; and
providing as an output the sensed bit of data.

### Claim 15 (depends on 14)

The method of claim 14, wherein generating the reference current includes generating the reference current that corresponds to a total resistance of a pair of the magnetic resistive elements coupled in parallel.

### Claim 16 (depends on 15)

The method of claim 15, wherein generating the reference current includes generating the reference current that further corresponds to a resistance of the resistive unit coupled in series with the magnetic resistive elements.

### Claim 17 (depends on 14)

The method of claim 14, wherein generating the reference current includes generating the reference current that corresponds to a total resistance of the resistive unit and the magnetic resistive element coupled in parallel.

### Claim 18 (depends on 14)

The method of claim 14, further comprising:
transmitting control signals to control a number of magnetic resistive elements to put those magnetic resistive elements into an anti-parallel state for contributing to generation of the reference current.

### Claim 19 (depends on 18)

The method of claim 18, wherein the control signals are applied to multiple transistors during initialization to set the magnetic resistive elements to the anti-parallel state, and wherein a single control signal is applied to one of the multiple transistors to generate the reference current.

### Claim 20 (depends on 1)

The memory device of claim 1, wherein the at least two transistors are selectively controllable so as to control contributions of the magnetic restrictive element to the reference current.