# US 10,319,419 B2 · Semiconductor memory device, and signal line layout structure thereof > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,319,419 B2 - Document ID: US10319419B2 - Status: Granted - Kind: B2 - Application number: 15/665,484 - Filed: 2017-08-01 - Published: 2018-06-14 - Granted: 2019-06-11 - Earliest claimed: 2016-12-09 - Assignees: SK hynix Inc. - Applicants: SK hynix Inc. - Inventors: Jong-Su Kim; Yeon-Gul Jung - Web page: https://patentgrep.com/patent/US10319419B2 ## CPC - G11C 7/1051: {Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits} - G11C 5/02: Disposition of storage elements, e.g. in the form of a matrix array - G11C 5/025: {Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device (geometrical lay-out of the components in integrated circuits, geometrical lay-out of the components in integrated circuits H10D89/10)} - G11C 5/063: {Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay} - G11C 7/1048: {Data bus control circuits, e.g. precharging, presetting, equalising} - G11C 7/1069: {I/O lines read out arrangements} - G11C 7/1078: {Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits} - G11C 7/08: Control thereof - G11C 7/10: Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers - G11C 2207/105: Aspects related to pads, pins or terminals - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract A memory device includes first and second memory blocks each including a memory cell array, a sub-word line drive region and a bit line sense amplifier region corresponding to the memory cell array, first and second data transmission lines disposed in the bit line sense amplifier region of each memory block, wherein the first and second data transmission lines extend on an identical row and transmit data of the memory cell array of the memory block, a row decoder configured to select one of the first and second memory blocks in response to a row address and enable a word line of the memory cell array included in the selected memory block, and a column decoder configured to generate, in response to a column address, first and second column select signals corresponding to the first and second data transmission lines of the bit line sense amplifier region. ## Claims ### Claim 1 A memory device comprising: first and second memory blocks, each including a memory cell array, a sub-word line drive region and a bit line sense amplifier region corresponding to the memory cell array; first and second data transmission lines disposed and extending on an identical row in the bit line sense amplifier region of the memory cell array, wherein the first and second data transmission lines transmit data of the memory cell array of the memory block; a row decoder configured to select one of the first and second memory blocks in response to a row address and enable a word line of the memory cell array included in the selected memory block; a column decoder configured to generate, in response to a column address, first and second column select signals corresponding to the first and second data transmission lines of the bit line sense amplifier region of the memory cell array included in the selected memory block; and a sense amplifier driver comprising: a drive signal generation unit configured to generate first and second drive signals respectively corresponding to first and second bit line sense amplifiers by combining a bit line sense amplifier enable signal with the first and second column select signals, and a drive unit configured to provide power line signals to the first and second bit line sense amplifiers in response to the first and second drive signals, respectively. ### Claim 2 (depends on 1) The memory device of claim 1, wherein the first and second data transmission lines form a symmetrical structure based on a center of one side of the memory cell array. ### Claim 3 (depends on 2) The memory device of claim 2, wherein the first and second data transmission lines are disposed in a row along the side of the memory cell array. ### Claim 4 (depends on 1) The memory device of claim 1, wherein: the first and second bit line sense amplifiers are disposed in the bit line sense amplifier region of each memory block and configured to sense/amplify the data of the memory cell array of the memory block and transmit the sensed/amplified data to the first and second data transmission lines, respectively. ### Claim 5 (depends on 4) The memory device of claim 4, wherein: the sense amplifier driver is configured to drive the first and second bit line sense amplifiers in response to the first and second column select signals and the bit line sense amplifier enable signal. ### Claim 6 (depends on 1) The memory device of claim 1, further comprising: first and second input/output switches disposed in the bit line sense amplifier region and coupled between the first and second data transmission lines and data input/output lines corresponding to the first and second data transmission lines. ### Claim 7 (depends on 6) The memory device of claim 6, wherein the first and second input/output switches respectively couple the first and second data transmission lines to the corresponding data input/output lines in response to the first and second column select signals. ### Claim 8 (depends on 6) The memory device of claim 6, wherein the first and second data transmission lines and the data input/output lines respectively include segment input/output lines and local input/output lines. ### Claim 9 (depends on 1) The memory device of claim 1, wherein the row decoder decodes the row address and generates first and second select signals respectively corresponding to the first and second memory blocks. ### Claim 10 (depends on 9) The memory device of claim 9, wherein the column decoder decodes the column address according to the first and second select signals and generates the first and second column select signals of the selected memory block from the first and second memory blocks. ### Claim 11 (depends on 9) The memory device of claim 9, wherein the first and second select signals include main or sub-word line drive signals corresponding to the first and second memory blocks. ### Claim 12 A memory device comprising: first and second memory blocks, each including a memory cell array defined by a sub-word line driver region and a bit line sense amplifier region; first and second data transmission lines disposed and extending on an identical row in the bit line sense amplifier region of the memory cell array; first and second bit line sense amplifiers disposed in the bit line sense amplifier region of the memory cell array and configured to sense/amplify data of the memory cell array and transmit the data to the first and second data transmission lines, respectively; and a sense amplifier driver comprising a drive signal generation unit configured to generate first and second drive signals respectively corresponding to the first and second bit line sense amplifiers by combining a bit line sense amplifier enable signal with first and second column select signals, and a drive unit configured to provide power line signals to the first and second bit line sense amplifiers in response to the first and second drive signals, respectively, wherein the first and second bit line sense amplifiers are selectively enabled according to a column address. ### Claim 13 (depends on 12) The memory device of claim 12, further comprising: a row decoder configured to select one of the first and second memory blocks by decoding a row address and enable a word line of the memory cell array included in the selected memory block. ### Claim 14 (depends on 13) The memory device of claim 13, further comprising: a column decoder configured to generate, by decoding the column address, the first and second column select signals, which correspond to the first and second data transmission lines of the memory cell array included in the selected memory block. ### Claim 15 (depends on 14) The memory device of claim 14, wherein: the sense amplifier driver is configured to drive the first and second bit line sense amplifiers in response to the first and second column select signals and the bit line sense amplifier enable signal. ### Claim 16 (depends on 14) The memory device of claim 14, further comprising: first and second input/output switches disposed in the bit line sense amplifier region and coupled between the first and second data transmission lines and data input/output lines corresponding to the first and second data transmission lines. ### Claim 17 (depends on 16) The memory device of claim 16, wherein the first and second input/output switches respectively couple the first and second data transmission lines to the corresponding data input/output lines in response to the first and second column select signals.