# US 10,319,418 B2 · Methods and systems for parallel column twist interleaving

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 10,319,418 B2
- Document ID: US10319418B2
- Status: Granted
- Kind: B2
- Application number: 15/918,395
- Filed: 2018-03-12
- Published: 2018-09-13
- Granted: 2019-06-11
- Earliest claimed: 2016-03-15
- Assignees: MaxLinear, Inc.
- Applicants: MaxLinear, Inc.
- Inventors: Jian-Hung Lin
- Web page: https://patentgrep.com/patent/US10319418B2

## CPC

- G11C 7/1012: {Data reordering during input/output, e.g. crossbars, layers of multiplexers, shifting or rotating}
- G11C 7/1057: {Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load}
- G11C 7/1084: {Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load}
- G11C 7/22: Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
- H03M 13/271: {Row-column interleaver with permutations, e.g. block interleaving with inter-row, inter-column, intra-row or intra-column permutations}
- H03M 13/6561: {Parallelized implementations}
- G11C 7/1006: {Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor}
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C)

## Abstract

Systems and methods are provided for enhanced parallel bit-interleaving. The parallel bit-interleaving may include, in each of a plurality of cycles, reading a number of bits from an input bitstream; processing the read bits, with the processing including applying a first adjustment to a first combination of bits that includes the read bits and additional bits, wherein each of the additional bits includes a previously read bit in the input bitstream or a pre-set bit; when one or more conditional criteria are met, applying a second adjustment to a second combination of bits that includes bits corresponding to previously read bits, wherein the conditional criteria include completing processing of a full column; writing into memory a number of bits corresponding to the first combination of bits and/or the second combination of bits; and reading from the memory a number of bits, for generating an output corresponding to the particular cycle.

## Claims

### Claim 1

A system configured for applying parallel bit-interleaving, the system comprising:
a memory that stores data during the parallel bit-interleaving;
an input circuit that reads from an input bitstream, in each particular cycle of a plurality of cycles of the parallel bit-interleaving, a number of bits;
one or more processing circuits that process the read bits, wherein the processing comprises:
applying a first adjustment to a first combination of bits that comprises the read bits and additional bits, wherein each of the additional bits comprises a previously read bit in the input bitstream or a pre-set bit;
when one or more conditional criteria are met, applying a second adjustment to a second combination of bits that comprises bits corresponding to previously read bits, wherein the one or more conditional criteria comprise completing processing of a full column;
writing into the memory a number of bits corresponding to the first combination of bits and/or the second combination of bits; and
reading from the memory a number of bits, for generating a cycle output corresponding to the particular cycle.

### Claim 2 (depends on 1)

The system of claim 1, wherein the memory comprises at least two separate memory portions configurable to operate concurrently during read and write operations.

### Claim 3 (depends on 2)

The system of claim 2, wherein the memory is configurable to enable, during the concurrent read and write operations, writing into one of the at least two separate memory portions while reading from another one of the at least two separate memory portions.

### Claim 4 (depends on 1)

The system of claim 1, comprising a control circuit that controls the parallel bit-interleaving.

### Claim 5 (depends on 4)

The system of claim 4, wherein the control circuit generates one or more control signals for controlling the parallel bit-interleaving.

### Claim 6 (depends on 4)

The system of claim 4, wherein the control circuit is configurable for controlling the parallel bit-interleaving based on an interleaving state machine.

### Claim 7 (depends on 4)

The system of claim 4, wherein the control circuit configures the parallel bit-interleaving based on one or more interleaving parameters.

### Claim 8 (depends on 7)

The system of claim 7, wherein the control circuit sets the number of bits read from the input bitstream based on a first interleaving parameter.

### Claim 9 (depends on 8)

The system of claim 8, wherein the control circuit determines the first interleaving parameter based on a level of parallelism for the parallel bit-interleaving.

### Claim 10 (depends on 8)

The system of claim 8, wherein the control circuit configures the one or more processing circuits for applying the first adjustment based on a second interleaving parameter.

### Claim 11 (depends on 10)

The system of claim 10, wherein the control circuit determines the second interleaving parameter based on one or more of:
the first interleaving parameter,
a column twist associated with a current column of an interleaving matrix used during the parallel bit-interleaving, and
a starting parameter for the current column in the interleaving matrix.

### Claim 12 (depends on 8)

The system of claim 8, wherein the control circuit sets the number of bits used in generating each cycle output based on a third interleaving parameter.

### Claim 13 (depends on 12)

The system of claim 12, wherein the control circuit determines the third interleaving parameter based on a number of columns of an interleaving matrix used during the parallel bit-interleaving.

### Claim 14 (depends on 12)

The system of claim 12, wherein the one or more processing circuits convert interleaved sets of bits each having a size based on the third interleaving parameter into sets of bits each having a size based on the first interleaving parameter.

### Claim 15

A method comprising:
applying parallel bit-interleaving to an input bitstream, wherein the applying of parallel bit-interleaving comprises, in each particular cycle of a plurality of cycles:
reading a number of bits from the input bitstream;
processing the read bits, the processing comprising applying a first adjustment to a first combination of bits that comprises the read bits and additional bits, wherein each of the additional bits comprises a previously read bit in the input bitstream or a pre-set bit;
when one or more conditional criteria are met, applying a second adjustment to a second combination of bits that comprises bits corresponding to previously read bits, wherein the one or more conditional criteria comprise completing processing of a full column;
writing into a memory a number of bits corresponding to the first combination of bits and/or the second combination of bits; and
reading from the memory a number of bits, for generating a cycle output corresponding to the particular cycle.

### Claim 16 (depends on 15)

The method of claim 15, comprising configuring the memory to enable concurrent read and write operations.

### Claim 17 (depends on 16)

The method of claim 16, wherein the concurrent read and write operations comprises writing into a first memory portion while reading from a second memory portion.

### Claim 18 (depends on 15)

The method of claim 15, comprising generating one or more control signals for controlling the parallel bit-interleaving.

### Claim 19 (depends on 15)

The method of claim 15, comprising controlling the parallel bit-interleaving based on preset interleaving state machine.

### Claim 20 (depends on 15)

The method of claim 15, comprising configuring the parallel bit-interleaving based on one or more interleaving parameters.

### Claim 21 (depends on 20)

The method of claim 20, wherein the one or more interleaving parameters comprise a first interleaving parameter, and comprising configuring the number of bits read from the output buffer based on the first interleaving parameter.

### Claim 22 (depends on 21)

The method of claim 21, comprising determining the first interleaving parameter based on a level of parallelism for the parallel bit-interleaving.

### Claim 23 (depends on 21)

The method of claim 21, wherein the one or more interleaving parameters comprise a second interleaving parameter, and comprising applying the first adjustment based on the second interleaving parameter.

### Claim 24 (depends on 23)

The method of claim 23, comprising determining the second interleaving parameter based on one or more of:
the first interleaving parameter,
a column twist associated with a current column of an interleaving matrix used during the parallel bit-interleaving, and
a starting parameter for the current column in the interleaving matrix.

### Claim 25 (depends on 21)

The method of claim 21, wherein the one or more interleaving parameters comprise a third interleaving parameter, and comprising determining the number of bits used in generating each cycle output based on the third interleaving parameter.

### Claim 26 (depends on 25)

The method of claim 25, comprising determining the third interleaving parameter based on a number of columns of an interleaving matrix used during the parallel bit-interleaving.

### Claim 27 (depends on 25)

The method of claim 25, comprising converting interleaved sets of bits each having a size based on the third interleaving parameter into sets of bits each having a size based on the first interleaving parameter.

### Claim 28 (depends on 15)

The method of claim 15, comprising generating an interleaved output bitstream corresponding to the input bitstream, based on the outputted bits from each of the plurality of cycles.