# US 10,319,362 B2 · High speed level shifter for high voltage applications

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- Number: US 10,319,362 B2
- Document ID: US10319362B2
- Status: Granted
- Kind: B2
- Application number: 15/793,537
- Filed: 2017-10-25
- Published: 2018-05-03
- Granted: 2019-06-11
- Earliest claimed: 2016-10-27
- Assignees: Texas Instruments Incorporated
- Applicants: Texas Instruments Incorporated
- Inventors: Ravikumar Pattipaka; Raja Sekhar Kanakamedala; Aravind Miriyala; Sandeep Kesrimal Oswal
- Web page: https://patentgrep.com/patent/US10319362B2

## CPC

- G10K 11/341: {Circuits therefor}
- B06B 1/0207: {Driving circuits (specially adapted for particular applications, see the relevant subclass, e.g. G01; circuits for steering transducer arrays G10K11/34; basic circuits H03)}
- G06F 1/3203: Power management, i.e. event-based initiation of a power-saving mode
- G10K 11/04: Acoustic filters {; Acoustic resonators}
- G11C 11/413: Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
- H03K 3/356113: {using additional transistors in the input circuit}
- H03K 17/08: Modifications for protecting switching circuit against overcurrent or overvoltage
- H03K 17/6871: {the output circuit comprising more than one controlled field-effect transistor}
- H03K 19/00361: {in field effect transistor circuits}
- H03K 19/018507: {Interface arrangements}
- H03K 17/56: by the use, as active elements, of semiconductor devices (using diodes H03K17/74)
- H03K 17/687: the devices being field-effect transistors
- H03K 2217/0063: High side switches, i.e. the higher potential [DC] or life wire [AC] being directly connected to the switch and not via the load
- G10K: SOUND-PRODUCING DEVICES; METHODS OR DEVICES FOR PROTECTING AGAINST, OR FOR DAMPING, NOISE OR OTHER ACOUSTIC WAVES IN GENERAL; ACOUSTICS NOT OTHERWISE PROVIDED FOR
- B06B: METHODS OR APPARATUS FOR GENERATING OR TRANSMITTING MECHANICAL VIBRATIONS OF INFRASONIC, SONIC, OR ULTRASONIC FREQUENCY, {e.g.} FOR PERFORMING MECHANICAL WORK IN GENERAL (for particular applications, see the relevant subclasses, e.g. B07B1/40, B23Q17/12, B24B31/06; measurement of mechanical vibrations G01H; in direction finding, locating, distance or velocity measuring G01S; {generating seismic energy G01V1/02}; control of mechanical vibrations in general G05D; sound-producing devices, e.g. bells, sirens, whistles G10K, {e.g. methods or devices for transmitting, conducting, or directing sound in general G10K11/00}; generation of electrical oscillations H03B; electromechanical resonators in general H03H; electromechanical transducers {for communication techniques, e.g. microphones, speakers} H04R)
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)

## Abstract

The disclosure provides a level shifter. The level shifter includes a first logic block that receives an input signal and generates a primary pulsed input. A first transistor is coupled to the first logic block and a first node. A gate terminal of the first transistor receives the primary pulsed input. A latch is coupled to the first node and a second node. A second logic block receives the input signal and generates a secondary pulsed input. A second transistor is coupled between the second logic block and the second node. A gate terminal of the second transistor receives the secondary pulsed input.

## Claims

### Claim 1

A level shifter comprising:
a first logic block configured to receive an input signal and configured to generate a primary pulsed input;
a first transistor coupled between the first logic block and a first node, a gate terminal of the first transistor configured to receive the primary pulsed input;
a latch coupled to the first node and a second node;
a second logic block configured to receive the input signal and configured to generate a secondary pulsed input;
a second transistor coupled between the second logic block and the second node, a gate terminal of the second transistor configured to receive the secondary pulsed input;
a third logic block coupled to the first node and configured to generate a first control signal; and
a third transistor whose gate terminal is configured to receive the first control signal and whose source terminal is coupled to a threshold voltage source, and a drain terminal of the third transistor is coupled to the first node.

### Claim 2 (depends on 1)

The level shifter of claim 1, wherein the primary pulsed input is generated at a rising edge of the input signal, and a duty cycle of the primary pulsed input is less than a duty cycle of the input signal.

### Claim 3 (depends on 1)

The level shifter of claim 1, wherein the secondary pulsed input is generated at a falling edge of the input signal, and a duty cycle of the secondary pulsed input is less than the duty cycle of the input signal.

### Claim 4 (depends on 1)

The level shifter of claim 1, wherein the first node and the second node are coupled to a voltage supply source.

### Claim 5 (depends on 1)

The level shifter of claim 1 further comprising:
a first capacitor coupled between the voltage supply source and the first node;
a second capacitor coupled between the first node and a fixed voltage source;
a third capacitor coupled between the voltage supply source and the second node; and
a fourth capacitor coupled between the second node and the fixed voltage source.

### Claim 6 (depends on 1)

The level shifter of claim 1 further comprising:
a fourth logic block coupled to the second node and configured to generate a second control signal; and
a fourth transistor whose gate terminal is configured to receive the second control signal and whose source terminal is coupled to the threshold voltage source, wherein a drain terminal of the fourth transistor is coupled to the second node.

### Claim 7 (depends on 1)

The level shifter of claim 1, wherein a source terminal of each of the first transistor and the second transistor is coupled to a low voltage terminal.

### Claim 8 (depends on 1)

The level shifter of claim 1, wherein the latch comprises:
a first inverter whose input terminal is coupled to the first node and whose output terminal is coupled to the second node; and
a second inverter whose input terminal is coupled to the second node and to the output terminal of the first inverter, and whose output terminal is coupled to the first node and the input terminal of the first inverter.

### Claim 9 (depends on 1)

The level shifter of claim 1, wherein when the first transistor is activated by the primary pulsed input and the second transistor is inactivated by the secondary pulsed input, a first voltage level and a second voltage level are stored on the latch.

### Claim 10

A method comprising:
generating a primary pulsed input in response to an input signal;
activating a first transistor when the primary pulsed input is at logic high;
generating a secondary pulsed input in response to the input signal;
inactivating a second transistor when the secondary pulsed input is at logic low;
transitioning a first node from a first voltage level to a second voltage level;
storing the first voltage level and the second voltage level in a latch coupled to the first node and a second node;
generating a first control signal when the first node transitions from the first voltage level to the second voltage level; and
activating a third transistor by the first control signal to maintain the first node at a fixed voltage level, wherein a source terminal of the third transistor is coupled to a threshold voltage source.

### Claim 11 (depends on 10)

The method of claim 10 further comprising:
generating a second control signal when the second node transitions from the first voltage level to the second voltage level; and
activating a fourth transistor by the second control signal to maintain the second node at the fixed voltage level, wherein a source terminal of the fourth transistor is coupled to the threshold voltage source.

### Claim 12 (depends on 10)

The method of claim 10 further comprising:
generating the primary pulsed input at a rising edge of the input signal, and a duty cycle of the primary pulsed input is less than a duty cycle of the input signal; and
generating the secondary pulsed input at a falling edge of the input signal, and a duty cycle of the secondary pulsed input is less than the duty cycle of the input signal.

### Claim 13 (depends on 10)

The method of claim 10 further comprising coupling the first node and the second node to a voltage supply source.

### Claim 14 (depends on 10)

The method of claim 10 further comprising coupling a set of capacitors between the first node, the second node, the voltage supply source and a fixed voltage source.

### Claim 15

An ultrasound system comprising a transmitter, the transmitter further comprising:
a level shifter configured to receive an input signal and configured to generate an output signal;
a driver coupled to the level shifter and configured to generate a drive signal in response to the output signal; and
a main transistor whose gate terminal is coupled to the driver, whose source terminal is coupled to a voltage supply source and whose drain terminal is coupled to a transducer, wherein the level shifter further comprising:
a first logic block configured to receive an input signal and configured to generate a primary pulsed input;
a first transistor coupled between the first logic block and a first node, a gate terminal of the first transistor configured to receive the primary pulsed input;
a latch coupled to the first node and a second node;
a second logic block configured to receive the input signal and configured to generate a secondary pulsed input;
a second transistor coupled between the second logic block and the second node, a gate terminal of the second transistor configured to receive the secondary pulsed input;
a third logic block coupled to the first node and configured to generate a first control signal; and
a third transistor whose gate terminal is configured to receive the first control signal and whose source terminal is coupled to a threshold voltage source, and a drain terminal of the third transistor is coupled to the first node.

### Claim 16 (depends on 15)

The ultrasound system of claim 15, wherein the level shifter further comprising:
a third logic block coupled to the first node and configured to generate a first control signal; and
a third transistor whose gate terminal is configured to receive the first control signal and whose source terminal is coupled to a threshold voltage source, wherein a drain terminal of the third transistor is coupled to the first node.

### Claim 17 (depends on 15)

The ultrasound system of claim 15, wherein the level shifter further comprising:
a fourth logic block coupled to the second node and configured to generate a second control signal; and
a fourth transistor whose gate terminal is configured to receive the second control signal and whose source terminal is coupled to the threshold voltage source, wherein a drain terminal of the fourth transistor is coupled to the second node.

### Claim 18 (depends on 15)

The ultrasound system of claim 15, wherein the primary pulsed input is generated at a rising edge of the input signal, and a duty cycle of the primary pulsed input is less than a duty cycle of the input signal, and wherein the secondary pulsed input is generated at a falling edge of the input signal, and a duty cycle of the secondary pulsed input is less than the duty cycle of the input signal.