# US 10,319,335 B2 · Image processor and display system having adaptive operational frequency range > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,319,335 B2 - Document ID: US10319335B2 - Status: Granted - Kind: B2 - Application number: 15/290,060 - Filed: 2016-10-11 - Published: 2017-04-27 - Granted: 2019-06-11 - Earliest claimed: 2015-10-27 - Assignees: Samsung Electronics Co., Ltd. - Applicants: Samsung Electronics Co., Ltd. - Inventors: Kyung-Min Park - Web page: https://patentgrep.com/patent/US10319335B2 ## CPC - G09G 5/006: {Details of the interface to the display terminal (specific for a display terminal using a CRT G09G1/167; using a flat panel G09G3/2096; circuits for interfacing with colour displays G09G5/04)} - G06T 1/20: Processor architectures; Processor configuration, e.g. pipelining - G09G 3/2096: {Details of the interface to the display terminal specific for a flat panel (suitable for both CRT and flat panel G09G5/006; specific for a CRT G09G1/167)} - G09G 5/363: {Graphics controllers} - G09G 5/393: Arrangements for updating the contents of the bit-mapped memory - G09G 5/395: Arrangements specially adapted for transferring the contents of the bit-mapped memory to the screen (G09G5/399 takes precedence) - G09G 2310/0267: Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays - G09G 2310/027: Details of drivers for data electrodes, the drivers handling digital grey scale data, e.g. use of D/A converters - G09G 2310/0297: Special arrangements with multiplexing or demultiplexing of display data in the drivers for data electrodes, in a pre-processing circuitry delivering display data to said drivers or in the matrix panel, e.g. multiplexing plural data signals to one D/A converter or demultiplexing the D/A converter output to multiple columns - G09G 2310/08: Details of timing specific for flat panels, other than clock recovery - G09G 2330/021: Power management, e.g. power saving - G09G 2340/0435: Change or adaptation of the frame rate of the video stream - G09G 2350/00: Solving problems of bandwidth in display systems - G09G 2360/12: Frame memory handling - G09G 2360/18: Use of a frame buffer in a display terminal, inclusive of the display panel - G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00) - G06T: IMAGE DATA PROCESSING OR GENERATION, IN GENERAL ## Abstract An image processor includes a frame buffer configured to collect an image data of pixels and configured to generate frame data, a display controller configured to generate the frame update command based on a vertical synchronizing signal and a frame per second signal representing a number of activating of the frame update signal in a second and an operating part configured to generate the vertical synchronizing signal and the image data. When the frame data is generated, the frame buffer activates a frame update signal in response to a frame update command and outputs the frame data. When the frame per second signal is less than a predetermined threshold voltage, the operating part sets a lower limit of a range of a frequency to a predetermined minimum frequency. ## Claims ### Claim 1 An image processor comprising: a frame buffer that collects image data of pixels and generates frame data, wherein when the frame data is generated, the frame buffer activates a frame update signal in response to a frame update command and outputs the frame data; a display controller that generates the frame update command based on a vertical synchronizing signal and a frame per second signal indicating a number per second of frame update signal activations; and a central processing unit (CPU) that generates the vertical synchronizing signal and collects the image data, wherein when the frame per second signal is less than a predetermined threshold value, the CPU identifies a first range of a first frequency at which the CPU operates but does not bound the first frequency by the first range until the frame per second signal equals or exceeds the predetermined threshold value. ### Claim 2 (depends on 1) The image processor of claim 1, wherein the CPU varies the first frequency based on a number of instructions processed by the CPU. ### Claim 3 (depends on 1) The image processor of claim 1, wherein: the CPU comprises a frequency controller, a graphic processing unit (GPU) and a multiplexer, the multiplexer outputs first data or second data as the image data based on a control signal, the first data and the control signal being generated by the CPU, and the second data being generated by the GPU, the frequency controller generates a first frequency control signal and a second frequency control signal based on the frame per second signal, and the CPU varies the first frequency according to the first frequency control signal and the GPU varies a second frequency at which the GPU operates according to the second frequency control signal. ### Claim 4 (depends on 3) The image processor of claim 3, wherein the frequency controller varies the first frequency control signal based on a number of instructions processed by the CPU and varies the second frequency control signal based on a number of instructions processed by the GPU. ### Claim 5 (depends on 3) The image processor of claim 3, wherein the frequency controller establishes a lower limit of the first range based on the second frequency. ### Claim 6 (depends on 5) The image processor of claim 5, wherein when the frame per second signal is less than the predetermined threshold value, the lower limit of the first range is set to a predetermined minimum frequency. ### Claim 7 (depends on 3) The image processor of claim 3, wherein the multiplexer outputs the first data as the image data when the control signal is activated and outputs the second data as the image data when the control signal is deactivated. ### Claim 8 (depends on 3) The image processor of claim 3, wherein the CPU activates the vertical synchronizing signal in a cycle. ### Claim 9 (depends on 8) The image processor of claim 8, wherein the cycle is 1/60 second. ### Claim 10 (depends on 1) The image processor of claim 1, wherein when the frame update command is applied and the frame data is generated, the frame buffer activates the frame update signal and the display controller increases the frame per second signal. ### Claim 11 (depends on 1) The image processor of claim 1, wherein when the frame update command is applied and the frame data is not generated, the frame buffer deactivates the frame update signal and the display controller does not increase the frame per second signal. ### Claim 12 (depends on 1) The image processor of claim 1, wherein the first range has a greater lower bound for the first frequency than does a second range which bounds the first frequency at the time the first range is identified. ### Claim 13 A display system comprising: an image processor that generates frame data and identifies, when a frequency for updating frame data is less than a predetermined threshold, a first range of a first frequency at which the image processor operates but does not bound the first frequency by the first range until the frequency for updating the frame data equals or exceeds the predetermined threshold; a timing controller that generates a data driver control signal and a scan driver control signal based on the frame data; a display panel comprising a plurality of pixels; a data driver that generates a plurality of data signals based on the data driver control signal and outputs the data signals to the pixels through a plurality of data signal lines; and a scan driver that generates a plurality of scan signals based on the scan driver control signal and outputs the scan signals to the pixels through a plurality of scan signal lines. ### Claim 14 (depends on 13) The display system of claim 13, wherein the image processor comprises: a frame buffer that collects image data of pixels and generates the frame data, wherein when the frame data is generated, the frame buffer activates a frame update signal in response to a frame update command and outputs the frame data; a display controller that generates the frame update command based on a vertical synchronizing signal, a frame per second signal indicating a number per second of frame update signal activations, and the frequency for updating the frame data; and a central processing unit (CPU) that generates the vertical synchronizing signal and the image data. ### Claim 15 (depends on 13) The display system of claim 13, wherein the first range has a greater lower bound for the first frequency than does a second range which bounds the first frequency at the time the first range is identified. ### Claim 16 A system comprising: a Central Processing Unit (CPU) that receives a frame per second signal indicating a number per second of frame update signal activations, operates in response to a first frequency, and generates a vertical synchronizing signal, a control signal, and a first data signal; a Graphics Processing Unit (GPU) that operates in response to a second frequency and generates a second data signal; and a multiplexer that receives the first data signal, the second data signal, and the control signal and selectively outputs either the first data signal or the second data signal in response to the control signal, wherein: the CPU comprises: a frame buffer that activates a frame update signal in response to a frame update command and outputs frame data; and a display controller that generates the frame update command based on the vertical synchronizing signal and the frame per second signal, and when the frame per second signal is less than a predetermined threshold value, the CPU identifies a first range of the first frequency but does not bound the first frequency by the first range until the frame per second signal equals or exceeds the predetermined threshold value. ### Claim 17 (depends on 16) The system of claim 16, wherein the second frequency is selected from a plurality of second frequencies and the first frequency falls within a plurality of ranges for the first frequency respectively corresponding to each one of the plurality of second frequencies. ### Claim 18 (depends on 16) The system of claim 16, wherein: the first frequency is based on a number of instructions processed by the CPU, and the second frequency is based on a number of instructions processed by the GPU. ### Claim 19 (depends on 16) The system of claim 16, wherein the CPU comprises a frequency controller providing a first frequency control signal to the CPU that defines the first frequency and providing a second frequency control signal to the GPU that defines the second frequency. ### Claim 20 (depends on 16) The system of claim 16, wherein the first range has a greater lower bound for the first frequency than does a second range which bounds the first frequency at the time the first range is identified.