# US 10,319,326 B2 · Display controller and display device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,319,326 B2 - Document ID: US10319326B2 - Status: Granted - Kind: B2 - Application number: 15/033,649 - Filed: 2016-01-28 - Published: 2018-04-05 - Granted: 2019-06-11 - Earliest claimed: 2015-12-31 - Assignees: Shenzhen China Star Optoelectronics Technology Co., Ltd. - Applicants: Shenzhen China Star Optoelectronics Technology Co., Ltd. - Inventors: Jhenwei He; Yu-Yeh Chen - Web page: https://patentgrep.com/patent/US10319326B2 ## CPC - G09G 3/3685: {Details of drivers for data electrodes} - G02F 1/133: Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements (arrangements or circuits for control of liquid crystal elements in a matrix, not structurally associated with these elements G09G3/36) - G09G 3/2096: {Details of the interface to the display terminal specific for a flat panel (suitable for both CRT and flat panel G09G5/006; specific for a CRT G09G1/167)} - G09G 5/18: Timing circuits for raster scan displays (specially adapted for television H04N {; synchronisation between the display unit and other display units, videodisc player G09G5/12}) - G09G 2340/02: Handling of images in compressed format, e.g. JPEG, MPEG - G09G 2340/0435: Change or adaptation of the frame rate of the video stream - G09G 2370/08: Details of image data interface between the display device controller and the data line driver circuit - G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00) - G02F: OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS ## Abstract This disclosure provides a display controller. The controller includes a timing controlling unit for providing a signal, a buffer unit for storing image information and outputting the image information processed with certain algorithm, a power management unit for managing the power of the display controller; and a data driving unit for providing a signal to a data line of a display device and controlling the image which is displayed. The timing controlling unit is electrically connected to the buffer unit. The buffer unit and the power management unit are integrated in a first circuit, and The timing controller and the data driving unit are integrated in a second circuit. The cost of the controller in thin disclosure is reduced. This disclosure also provides a display device with the above-mentioned display controller. ## Claims ### Claim 1 A display controller, comprising: a timing controlling unit for providing a signal; a buffer unit for storing image information and outputting the image information processed with certain algorithm; a power management unit for managing the power of the display controller; and a data driving unit for providing a signal to a data line of a display device and controlling the image which is displayed, wherein the timing controlling unit is electrically connected to the buffer unit, the buffer unit and the power management unit are integrated in a first circuit, and the timing controlling unit and the data driving unit are integrated in a second circuit, wherein, the buffer unit comprises a plurality of pins configured for connecting to the timing controlling unit, a plurality of lines are connected between the pins of the buffer unit and the timing controlling unit, and a number of the lines is less than a number of the pins configured for connecting to the timing controlling unit such that at least one of the pins configured for connecting to the timing controlling unit is floated. ### Claim 2 (depends on 1) The display controller according to claim 1, wherein the timing controlling unit communicates data signal to the buffer unit. ### Claim 3 (depends on 1) The display controller according to claim 1, wherein the timing controlling unit further comprises a data processing module for compression coding and decoding of the signal. ### Claim 4 (depends on 3) The display controller according to claim 3, wherein the data processing module is electrically connected to the buffer unit. ### Claim 5 (depends on 1) The display controller according to claim 1, wherein the buffer unit is a Double Data Rate SDRAM or a flash memory. ### Claim 6 A display device, comprising a display controller and a display panel, wherein the display controller comprises: a timing controlling unit, for providing at least a signal; a buffer unit for storing image information and outputting the image information processed with certain algorithm; a power management unit for managing the power of the display controller; and a data driving unit for providing a signal to a data line of a display device and controlling the image which is displayed, wherein the timing controlling unit is electrically connected to the buffer unit, the buffer unit and the power management unit are integrated in a first circuit, and the timing controlling unit and the data driving unit are integrated in a second circuit, wherein, the buffer unit comprises a plurality of pins configured for connecting to the timing controlling unit, a plurality of lines are connected between the pins of the buffer unit and the timing controlling unit, and a number of the lines is less than a number of the pins configured for connecting to the timing controlling unit such that at least one of the pins configured for connecting to the timing controlling unit is floated. ### Claim 7 (depends on 6) The display controller according to claim 6, wherein the timing controlling unit communicates data signal to the buffer unit. ### Claim 8 (depends on 6) The display controller according to claim 6, wherein the timing controlling unit further comprises a data processing module for compression coding and decoding of the signal. ### Claim 9 (depends on 8) The display controller according to claim 8, wherein the data processing module is electrically connected to the buffer unit. ### Claim 10 (depends on 6) The display controller according to claim 6, wherein the buffer unit is a Double Data Rate SDRAM or a flash memory.