# US 10,319,324 B2 · Shift registers, driving methods, gate driving circuits and display apparatuses with reduced shift register output signal voltage switching time

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- Number: US 10,319,324 B2
- Document ID: US10319324B2
- Status: Granted
- Kind: B2
- Application number: 15/680,452
- Filed: 2017-08-18
- Published: 2018-07-12
- Granted: 2019-06-11
- Earliest claimed: 2017-01-06
- Assignees: Boe Technology Group Co., Ltd.; Hefei Boe Optoelectronics Technology Co., Ltd.
- Applicants: Boe Technology Group Co., Ltd.; Hefei Boe Optoelectronics Technology Co., Ltd.
- Inventors: Xianjie Shao; Junsheng Chen
- Web page: https://patentgrep.com/patent/US10319324B2

## CPC

- G09G 3/3677: {suitable for active matrices only}
- G11C 19/28: using semiconductor elements (G11C19/14, G11C19/36 take precedence)
- G11C 19/287: {Organisation of a multiplicity of shift registers}
- G09G 3/3648: {using an active matrix (G09G3/367 - G09G3/3696 take precedence)}
- G09G 2300/0408: Integration of the drivers onto the display substrate
- G09G 2310/0286: Details of a shift registers arranged for use in a driving circuit
- G09G 2310/08: Details of timing specific for flat panels, other than clock recovery
- G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00)
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

The embodiments of the present application provide a shift register and a method for driving the same. The shift register comprises: an input unit, a pull-up unit, a reset unit, a pull-down control unit, a pull-down unit and a pull-up holding unit. The input unit is configured to couple a first voltage terminal to a pull-up point. The pull-up unit is configured to couple a clock signal terminal to an output signal terminal. The reset unit is configured to couple a second voltage terminal to the pull-up point. The pull-down control unit is configured to selectively couple one of the second voltage terminal and a third voltage terminal to a pull-down point. The pull-down unit is configured to couple the second voltage terminal to the pull-up point and the output signal terminal. The pull-up holding unit is configured to couple a fourth voltage terminal to the pull-up point.

## Claims

### Claim 1

A shift register, comprising:
an input unit coupled to an input signal terminal, a first voltage terminal and a pull-up point, and configured to couple the first voltage terminal to the pull-up point under a control of an input signal from the input signal terminal;
a pull-up unit coupled to the pull-up point, a clock signal terminal and an output signal terminal, and configured to couple the clock signal terminal to the output signal terminal under a control of a voltage at the pull-up point;
a reset unit coupled to a reset signal terminal, a second voltage terminal and the pull-up point, and configured to couple the second voltage terminal to the pull-up point under a control of a reset signal from the reset signal terminal;
a pull-down control unit coupled to the pull-up point, the second voltage terminal, a third voltage terminal and the pull-down point, and configured to selectively couple one of the second voltage terminal and the third voltage terminal to the pull-down point under a control of the voltage at the pull-up point;
a pull-down unit coupled to the pull-down point, the second voltage terminal, the pull-up point and the output signal terminal, and configured to couple the second voltage terminal to the pull-up point and the output signal terminal under a control of a voltage at the pull-down point; and
a pull-up holding unit coupled to a pull-up holding signal terminal, a fourth voltage terminal and the pull-up point, and configured to couple the fourth voltage terminal to the pull-up point under a control of a pull-up holding signal from the pull-up holding signal terminal, to maintain the voltage at the pull-up point to be valid,
wherein the pull-up unit comprises a third transistor, which has a control electrode coupled to the pull-up point, a first electrode coupled to the clock signal terminal and a second electrode coupled to the output signal terminal, and
wherein the valid voltage maintained at the pull-up point controls the third transistor to be turned on so as to couple the clock signal terminal to the output signal terminal when an invalid signal is being applied to the clock signal terminal, and controls the output signal terminal to output an invalid signal.

### Claim 2 (depends on 1)

The shift register according to claim 1, wherein the pull-up holding unit is coupled to the pull-up holding signal terminal and the pull-up point, and is configured to couple the pull-up holding signal terminal to the pull-up point under a control of the pull-up holding signal from the pull-up holding signal terminal.

### Claim 3 (depends on 1)

The shift register according to claim 1, wherein the pull-up holding unit comprises a first transistor having a control electrode coupled to the pull-up holding signal terminal, a first electrode coupled to the fourth voltage terminal and a second electrode coupled to the pull-up point.

### Claim 4 (depends on 3)

The shift register according to claim 3, wherein the input unit comprises a second transistor having a control electrode coupled to the input signal terminal, a first electrode coupled to the first voltage terminal and a second electrode coupled to the pull-up point.

### Claim 5 (depends on 1)

The shift register according to claim 1, wherein the pull-up unit further comprises a first capacitor, wherein the first capacitor has two terminals coupled between the control electrode and the second electrode of the third transistor.

### Claim 6 (depends on 5)

The shift register according to claim 5, wherein the reset unit comprises a fourth transistor having a control electrode coupled to the reset signal terminal, a first electrode coupled to the second voltage terminal and a second electrode coupled to the pull-up point.

### Claim 7 (depends on 6)

The shift register according to claim 6, wherein the pull-down control unit comprises a fifth transistor, a sixth transistor, a seventh transistor and an eighth transistor, wherein:
the fifth transistor has a control electrode and a first electrode coupled to the third voltage terminal and a second electrode coupled to a control terminal of the sixth transistor;
the sixth transistor has a first electrode coupled to the third voltage terminal and a second electrode coupled to the pull-down point;
the seventh transistor has a control electrode coupled to the pull-up point, a first electrode coupled to the second voltage terminal and a second electrode coupled to the control electrode of the sixth transistor; and
the eighth transistor has a control electrode coupled to the pull-up point, a first electrode coupled to the second voltage terminal and a second electrode coupled to the pull-down point.

### Claim 8 (depends on 7)

The shift register according to claim 7, wherein the pull-down unit comprises a ninth transistor and a tenth transistor, wherein:
the ninth transistor has a control electrode coupled to the pull-down point, a first electrode coupled to the second voltage terminal and a second electrode coupled to the pull-up point; and
the tenth transistor has a control electrode coupled to the pull-down point, a first electrode coupled to the second voltage terminal and a second electrode coupled to the output signal terminal.

### Claim 9 (depends on 1)

A method for driving the shift register according to claim 1, the method comprising:
applying a valid signal to the input signal terminal, and applying an invalid signal to the clock signal terminal and the reset signal terminal, so that a voltage at the pull-up point is valid to control the pull-up unit to couple the clock signal terminal to the output signal terminal and the output signal terminal to output an invalid signal;
applying a valid signal to the clock signal terminal, and applying an invalid signal to the input signal terminal and the reset signal terminal, so that the voltage at the pull-up point is valid to control the pull-up unit to couple the clock signal terminal to the output signal terminal and the output signal terminal to output a valid signal;
applying an invalid signal to the input signal terminal, the clock signal terminal and the reset signal terminal, and maintaining the voltage at the pull-up point to be valid, to control the pull-up unit to couple the clock signal terminal to the output signal terminal and the output signal terminal to output an invalid signal;
applying a valid signal to the reset signal terminal and applying an invalid signal to the input signal terminal, so that the voltage at the pull-up point is invalid to control the pull-down unit to couple the second voltage terminal to the pull-up point and the output signal terminal, and the output signal terminal to output an invalid signal; and
applying an invalid signal to the input signal terminal and the reset signal terminal, so that the voltage at the pull-up point is invalid to control the pull-down unit to couple the second voltage terminal to the pull-up point and the output signal terminal, and the output signal to output an invalid signal.

### Claim 10 (depends on 9)

The method according to claim 9, wherein maintaining the voltage at the pull-up point to be valid comprises: applying a valid signal to the pull-up holding signal terminal to control the pull-up holding unit to couple the fourth voltage terminal to the pull-up point.

### Claim 11 (depends on 1)

A gate driving circuit comprising a plurality of cascaded shift registers according to claim 1, wherein:
in every three stages of shift registers,
a first stage of shift register has an output signal terminal coupled to an input signal terminal of a second stage of shift register, a pull-up holding signal terminal coupled to an output signal terminal of the second stage of shift register and a reset signal terminal coupled to an output signal terminal of a third stage of shift register;
a clock signal terminal of the first stage of shift register and a clock signal terminal of the third stage of shift register are coupled to a first clock signal source; and
a clock signal terminal of the second stage of shift register is coupled to a second clock signal source.

### Claim 12 (depends on 11)

A display apparatus comprising the gate driving circuit according to claim 11.