# US 10,319,321 B2 · GOA circuit and a liquid crystal display > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,319,321 B2 - Document ID: US10319321B2 - Status: Granted - Kind: B2 - Application number: 15/327,637 - Filed: 2017-01-16 - Published: 2018-07-26 - Granted: 2019-06-11 - Earliest claimed: 2016-12-30 - Assignees: Shenzhen China Star Optoelectronics Technology Co., Ltd. - Applicants: Shenzhen China Star Optoelectronics Technology Co., Ltd. - Inventors: Longqiang Shi - Web page: https://patentgrep.com/patent/US10319321B2 ## CPC - G09G 3/3674: {Details of drivers for scan electrodes} - G02F 1/13306: {Circuit arrangements or driving methods for the control of single liquid crystal cells (G02F1/132, G02F1/133382 take precedence)} - G09G 3/36: using liquid crystals - G09G 3/3677: {suitable for active matrices only} - G09G 2300/0408: Integration of the drivers onto the display substrate - G09G 2310/0264: Details of driving circuits - G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00) - G02F: OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS ## Abstract The present application discloses a GOA circuit and a liquid crystal display including: a pull-up circuit, including a first switching transistor; a pull-down circuit, including a second switching transistor; a scanning output terminal coupled to the second connecting terminal of the first switching transistor, and a first connecting terminal of the second switching transistor; and a clamping circuit, coupling to the second connecting terminals of the first switching transistor and the second switching transistor, and coupling to the control terminals of the first switching transistor and the second switching transistor, when the scanning output terminal outputs a first electric level, controlling the electric level of the control terminal of the second switching transistor to be lower than the electric level of the second connecting terminal of the second switching transistor. The present application prevents the transistor from erroneously turning on or off due to the turn on threshold shift. ## Claims ### Claim 1 A liquid crystal display comprising a GOA circuit, wherein the GOA circuit comprises: a pull-up circuit, comprising a first switching transistor; a pull-down circuit, comprising a second switching transistor; a scanning output terminal coupled to a second connecting terminal of the first switching transistor, and a first connecting terminal of the second switching transistor; a downstream circuit comprising a ninth switching transistor with a control terminal coupled to a control terminal of the first switching transistor, a first connecting terminal coupled to a first connecting terminal of the first switching transistor and a second connecting terminal coupled to a stage transmission output terminal; and a clamping circuit, coupling to the second connecting terminal of the first switching transistor and a second connecting terminal of the second switching transistor, and coupling to the control terminal of the first switching transistor and a control terminal of the second switching transistor; when the scanning output terminal outputs a first electric level, controlling an electric level of the control terminal of the second switching transistor to be lower than an electric level of the second connecting terminal of the second switching transistor, and when the scanning output terminal outputs a second electric level, controlling an electric level of the control terminal of the first switching transistor to be lower than an electric level of the second connecting terminal of the first switching transistor, and the first electric level to be higher than the second electric level; wherein the clamping circuit comprises: a first clamping terminal, inputting a third electric level coupled to the second connecting terminal of the second switching transistor; and a second clamping terminal, inputting a fourth electric level coupled to the control terminal of the first switching transistor and coupled to the control terminal of the second switching transistor through a control circuit; wherein the third electric level is higher than the fourth electric level; the control circuit is adapted to control the control terminal of the second switching transistor to receive the fourth electric level of the second clamping terminal when the scanning output terminal outputs the first electric level, and to control the control terminal of the first switching transistor to receive the fourth electric level of the second clamping terminal when the scanning output terminal outputs the second electric level; wherein the control circuit comprises: a third switching transistor having a control terminal connected to the control terminal of the first switching transistor, a first connecting terminal connected to the control terminal of the second switching transistor and a second connecting terminal connected to the second clamping terminal; a fourth switching transistor having a control terminal and a first connecting terminal connected to a third clamping terminal and a second connecting terminal connected to the control terminal of the second switching transistor, wherein a high electric level is inputted to the third clamping terminal; a fifth switching transistor having a control terminal connected to the control terminal of the second switching transistor and a second connecting terminal connected to the second clamping terminal; and a sixth switching transistor having a control terminal connected to the control terminal of the second switching transistor, a first connecting terminal connected to the control terminal of the first switching transistor and a second connecting terminal connected to a first connecting terminal of the fifth switching transistor; wherein the control circuit further comprises a first capacitor connected between the first connecting terminal and the second connecting terminal of the sixth switching transistor; and when the control terminal of the second switching transistor is controlled to receive the fourth electric level of the second clamping terminal, the first capacitor maintains the sixth transistor to be turned off. ### Claim 2 (depends on 1) The liquid crystal display according to claim 1, wherein the GOA circuit further comprises: a pull-up control circuit, comprising: a seventh switching transistor having a control terminal to which is inputted a clock signal, and a first connecting terminal to which is inputted a stage transmission signal; an eighth switching transistor having a control terminal to which is inputted the clock signal and a first connecting terminal coupled to a second connecting terminal of the seventh switching transistor and a second connecting terminal coupled to the control terminal of the first switching transistor. ### Claim 3 (depends on 2) The liquid crystal display according to claim 2, wherein the pull-up control circuit further comprises a second capacitor coupled between the first connecting terminal and the second connecting terminal of the eighth switching transistor. ### Claim 4 A GOA circuit comprising: a pull-up circuit, comprising a first switching transistor; a pull-down circuit, comprising a second switching transistor; a scanning output terminal coupled to a second connecting terminal of the first switching transistor, and a first connecting terminal of the second switching transistor; a clamping circuit, coupling to the second connecting terminal of the first switching transistor and a second connecting terminal of the second switching transistor, and coupling to the control terminal of the first switching transistor and a control terminal of the second switching transistor; and a downstream circuit comprising a ninth switching transistor with a control terminal coupled to a control terminal of the first switching transistor, a first connecting terminal coupled to a first connecting terminal of the first switching transistor and a second connecting terminal coupled to a stage transmission output terminal; when the scanning output terminal outputs a first electric level, controlling an electric level of the control terminal of the second switching transistor to be lower than an electric level of the second connecting terminal of the second switching transistor, and when the scanning output terminal outputs a second electric level, controlling an electric level of the control terminal of the first switching transistor to be lower than an electric level of the second connecting terminal of the first switching transistor, and the first electric level to be higher than the second electric level; wherein the clamping circuit comprises: a first clamping terminal, inputting a third electric level coupled to the second connecting terminal of the second switching transistor; and a second clamping terminal, inputting a fourth electric level coupled to the control terminal of the first switching transistor and coupled to the control terminal of the second switching transistor through a control circuit; wherein the third electric level is higher than the fourth electric level; the control circuit is adapted to control the control terminal of the second switching transistor to receive the fourth electric level of the second clamping terminal when the scanning output terminal outputs the first electric level, and to control the control terminal of the first switching transistor to receive the fourth electric level of the second clamping terminal when the scanning output terminal outputs the second electric level; wherein the control circuit comprises: a third switching transistor having a control terminal connected to the control terminal of the first switching transistor, a first connecting terminal connected to the control terminal of the second switching transistor and a second connecting terminal connected to the second clamping terminal; a fourth switching transistor having a control terminal and a first connecting terminal connected to a third clamping terminal and a second connecting terminal connected to the control terminal of the second switching transistor, wherein a high electric level is inputted to the third clamping terminal; a fifth switching transistor having a control terminal connected to the control terminal of the second switching transistor and a second connecting terminal connected to the second clamping terminal; and a sixth switching transistor having a control terminal connected to the control terminal of the second switching transistor, a first connecting terminal connected to the control terminal of the first switching transistor and a second connecting terminal connected to a first connecting terminal of the fifth switching transistor; wherein the control circuit further comprises a first capacitor connected between the first connecting terminal and the second connecting terminal of the sixth switching transistor; and when the control terminal of the second switching transistor is controlled to receive the fourth electric level of the second clamping terminal, the first capacitor maintains the sixth transistor to be turned off. ### Claim 5 (depends on 4) The GOA circuit according to claim 4, wherein the GOA circuit further comprises: a pull-up control circuit, comprising: a seventh switching transistor having a control terminal to which is inputted a clock signal, and a first connecting terminal to which is inputted a stage transmission signal; an eighth switching transistor having a control terminal to which is inputted the clock signal and a first connecting terminal coupled to a second connecting terminal of the seventh switching transistor and a second connecting terminal coupled to the control terminal of the first switching transistor. ### Claim 6 (depends on 5) The GOA circuit according to claim 5, wherein the pull-up control circuit further comprises a second capacitor coupled between the first connecting terminal and the second connecting terminal of the eighth switching transistor. ### Claim 7 (depends on 6) The GOA circuit according to claim 6, wherein the first connecting terminal of the eighth switching transistor is further coupled to the second connecting terminal of the sixth switching transistor. ### Claim 8 A liquid crystal display comprising a GOA circuit, wherein the GOA circuit comprises: a pull-up circuit, comprising a first switching transistor; a pull-down circuit, comprising a second switching transistor; a scanning output terminal coupled to a second connecting terminal of the first switching transistor, and a first connecting terminal of the second switching transistor; a clamping circuit, coupling to the second connecting terminal of the first switching transistor and a second connecting terminal of the second switching transistor, and coupling to the control terminal of the first switching transistor and a control terminal of the second switching transistor; a downstream circuit comprising a ninth switching transistor with a control terminal coupled to a control terminal of the first switching transistor, a first connecting terminal coupled to a first connecting terminal of the first switching transistor and a second connecting terminal coupled to a stage transmission output terminal; and a pull-up control circuit, comprising a seventh switching transistor having a control terminal to which is inputted a clock signal and a first connecting terminal to which is inputted a stage transmission signal, and an eighth switching transistor having a control terminal to which is inputted the clock signal and a first connecting terminal coupled to a second connecting terminal of the seventh switching transistor and a second connecting terminal coupled to the control terminal of the first switching transistor; the pull-up control circuit further comprises a second capacitor coupled between the first connecting terminal and the second connecting terminal of the eighth switching transistor, and the first connecting terminal of the eighth switching transistor is further coupled to the second connecting terminal of the sixth switching transistor; when the scanning output terminal outputs a first electric level, controlling an electric level of the control terminal of the second switching transistor to be lower than an electric level of the second connecting terminal of the second switching transistor, and when the scanning output terminal outputs a second electric level, controlling an electric level of the control terminal of the first switching transistor to be lower than an electric level of the second connecting terminal of the first switching transistor, and the first electric level to be higher than the second electric level; wherein the clamping circuit comprises: a first clamping terminal, inputting a third electric level coupled to the second connecting terminal of the second switching transistor; and a second clamping terminal, inputting a fourth electric level coupled to the control terminal of the first switching transistor and coupled to the control terminal of the second switching transistor through a control circuit; wherein the third electric level is higher than the fourth electric level; the control circuit is adapted to control the control terminal of the second switching transistor to receive the fourth electric level of the second clamping terminal when the scanning output terminal outputs the first electric level, and to control the control terminal of the first switching transistor to receive the fourth electric level of the second clamping terminal when the scanning output terminal outputs the second electric level; wherein the control circuit comprises: a third switching transistor having a control terminal connected to the control terminal of the first switching transistor, a first connecting terminal connected to the control terminal of the second switching transistor and a second connecting terminal connected to the second clamping terminal; a fourth switching transistor having a control terminal and a first connecting terminal connected to a third clamping terminal and a second connecting terminal connected to the control terminal of the second switching transistor, wherein a high electric level is inputted to the third clamping terminal; a fifth switching transistor having a control terminal connected to the control terminal of the second switching transistor and a second connecting terminal connected to the second clamping terminal; and a sixth switching transistor having a control terminal connected to the control terminal of the second switching transistor, a first connecting terminal connected to the control terminal of the first switching transistor and a second connecting terminal connected to a first connecting terminal of the fifth switching transistor; wherein the control circuit further comprises a first capacitor connected between the first connecting terminal and the second connecting terminal of the sixth switching transistor; and when the control terminal of the second switching transistor is controlled to receive the fourth electric level of the second clamping terminal, the first capacitor maintains the sixth transistor to be turned off. ### Claim 9 (depends on 1) The liquid crystal display according to claim 1, wherein the GOA circuit further comprises: wherein the pull-up circuit further comprises a third capacitor coupled between the control terminals of the first switching transistor, the ninth switching transistor, and the second connecting terminal of the first switching transistor. ### Claim 10 (depends on 4) The liquid crystal display according to claim 4, wherein the GOA circuit further comprises: wherein the pull-up circuit further comprises a third capacitor coupled between the control terminals of the first switching transistor, the ninth switching transistor, and the second connecting terminal of the first switching transistor. ### Claim 11 (depends on 8) The liquid crystal display according to claim 8, wherein the GOA circuit further comprises: wherein the pull-up circuit further comprises a third capacitor coupled between the control terminals of the first switching transistor, the ninth switching transistor, and the second connecting terminal of the first switching transistor.