# US 10,319,283 B2 · Gate driving circuit and display device including the same

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- Number: US 10,319,283 B2
- Document ID: US10319283B2
- Status: Granted
- Kind: B2
- Application number: 15/371,985
- Filed: 2016-12-07
- Published: 2017-06-15
- Granted: 2019-06-11
- Earliest claimed: 2015-12-15
- Assignees: LG Display Co., Ltd.
- Applicants: LG Display Co., Ltd.
- Inventors: Byungil Kim; Seokhwan Choi
- Web page: https://patentgrep.com/patent/US10319283B2

## CPC

- G09G 3/2092: {Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto (suitable for both CRT and flat panel G09G5/003; specific for a CRT G09G1/165)}
- G09G 3/20: for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix {no fixed position being assigned to or needed to be assigned to the individual characters or partial characters}
- G11C 19/28: using semiconductor elements (G11C19/14, G11C19/36 take precedence)
- G09G 3/3677: {suitable for active matrices only}
- G09G 2300/0408: Integration of the drivers onto the display substrate
- G09G 2300/043: Compensation electrodes or other additional electrodes in matrix displays related to distortions or compensation signals, e.g. for modifying TFT threshold voltage in column driver
- G09G 2300/0809: Several active elements per pixel in active matrix panels
- G09G 2300/0819: used for counteracting undesired variations, e.g. feedback or autozeroing
- G09G 2310/0267: Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
- G09G 2310/0286: Details of a shift registers arranged for use in a driving circuit
- G09G 2310/0291: Details of output amplifiers or buffers arranged for use in a driving circuit
- G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00)
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

Provided are a gate driving circuit and a display device including the same. The gate driving circuit according to an embodiment includes a shift register including a plurality of stages. An nth stage of the stages includes a latch control circuit including a first NMOS transistor connected to a QB node, a second NMOS transistor connected to a Q node, and a third NMOS transistor having a gate electrode to which a first clock is input and connected to the first and second NMOS transistors, where n is a positive integer. A latch is connected between the Q and QB nodes. A transmission gate is connected to the Q and QB nodes. In the gate driving circuit, output signals of a previous stage and a following stage are controlled so as to be synchronized with the first clock to suppress a glitch.

## Claims

### Claim 1

A gate driving circuit comprising:
a shift register including a plurality of stages,
wherein an nth stage of the plurality of stages includes:
a latch control circuit including a first NMOS transistor connected to a QB node, a second NMOS transistor connected to a Q node, and a third NMOS transistor having a gate electrode to which a first clock is input and connected to the first NMOS transistor and the second NMOS transistor;
a latch connected between the Q node and the QB node; and
a buffer including a transmission gate connected to the Q node and the QB node and having a source electrode to which a second clock is input,
wherein n is a positive integer,
wherein in the latch control circuit, the first NMOS transistor includes a gate electrode to which a first carry signal from an n−1th stage is input and a drain electrode connected to the QB node, and the second NMOS transistor includes a gate electrode to which a second carry signal from an n+1th stage is input and a drain electrode connected to the Q node, and
wherein the first carry signal from an n−1th stage is not an inverting signal of the second carry signal from an n+1th stage.

### Claim 2 (depends on 1)

The gate driving circuit according to claim 1, wherein the third NMOS transistor includes:
a source electrode connected to a low voltage power line, and
a drain electrode connected to a source electrode of the first NMOS transistor and a source electrode of the second NMOS transistor.

### Claim 3 (depends on 1)

The gate driving circuit according to claim 1, wherein the latch includes a first inverter and a second inverter connected to each other in a closed-loop feedback circuit,
wherein the first inverter includes:
a fourth NMOS transistor having a gate electrode connected to the Q node, a drain electrode connected to the QB node, and a source electrode connected to a low voltage power line; and
a first PMOS transistor having a gate electrode connected to the Q node, a drain electrode connected to the QB node, and a source electrode connected to a high voltage power line, and
wherein the second inverter includes:
a fifth NMOS transistor having a gate electrode connected to the QB node, a drain electrode connected to the Q node, and a source electrode connected to the low voltage power line; and
a second PMOS transistor having a gate electrode connected to the QB node, a drain electrode connected to the Q node, and a source electrode connected to the high voltage power line.

### Claim 4 (depends on 1)

The gate driving circuit according to claim 1, wherein the buffer includes:
a pull-down transistor having a gate electrode connected to the QB node,
a drain electrode connected to a low voltage power line, and
a source electrode connected to a drain electrode of the transmission gate.

### Claim 5 (depends on 4)

The gate driving circuit according to claim 4, wherein the transmission gate includes:
a sixth NMOS transistor having a gate electrode to which a signal of the Q node is input and a drain electrode connected to the drain electrode of the pull-down transistor and an output node; and
a third PMOS transistor having a gate electrode to which a signal of the QB node is input and a drain electrode connected to the drain electrode of the pull-down transistor and the output node.

### Claim 6 (depends on 1)

The gate driving circuit according to claim 1, wherein the first carry signal and the second carry signal are synchronized with the first clock.

### Claim 7 (depends on 6)

The gate driving circuit according to claim 6, wherein a first pulse of the first carry signal and a second pulse of the second carry signal occur at different times and correspond to different pulses of the first clock, and
wherein a leading edge of a pulse of the first carry signal is aligned with a leading edge of a pulse of the first clock, and a leading edge of a pulse of the second carry signal is aligned with a leading edge of another pulse of the first clock.

### Claim 8 (depends on 1)

The gate driving circuit according to claim 1, wherein an output of the nth stage is synchronized with a pulse of the second clock and supplied to a gate line.

### Claim 9

A gate driving circuit comprising:
a shift register configured to a plurality of stages,
wherein an nth stage of the plurality of stages includes:
a latch control circuit configured to control, based on a first clock, a first carry signal received from an n−1th stage, and a second carry signal received from an n+1th stage, a QB node to have a low voltage when the first clock and the first carry signal have high voltages, and a Q node to have a low voltage when the first clock and the second carry signal have high voltages;
a latch connected between the Q node and the QB node; and
a buffer configured to increase an output voltage to be synchronized with a second clock when the Q node has a high voltage and decrease the output voltage when the QB node has a high voltage,
wherein n is a positive integer, and
wherein the first carry signal from an n−1th stage is not an inverting signal of the second carry signal from an n+1th stage.

### Claim 10 (depends on 9)

The gate driving circuit according to claim 9, wherein the latch control circuit is configured to receive the first clock and suppress a noise of an output voltage generated by at least one of a noise signal in the first carry signal and a noise signal in the second carry signal.

### Claim 11 (depends on 9)

The gate driving circuit according to claim 9, wherein the latch control circuit is configured to be synchronized with the first carry signal and suppress an increase in voltage of the Q node caused by a noise signal in the first carry signal.

### Claim 12 (depends on 9)

The gate driving circuit according to claim 9, wherein the latch control circuit is configured to be synchronized with the second carry signal and suppress a decrease in voltage of the QB node caused by a noise signal in the second carry signal.

### Claim 13 (depends on 9)

The gate driving circuit according to claim 9, wherein the latch controls the output voltage by inverting the voltage of the Q node and the voltage of the QB node.

### Claim 14 (depends on 9)

The gate driving circuit according to claim 9, wherein the buffer includes a pull-down transistor configured to decrease the output voltage by discharging an output node so as to correspond to the voltage of the QB node.