# US 10,319,274 B2 · Shift register unit, driving method thereof, gate driving circuit and display device

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- Number: US 10,319,274 B2
- Document ID: US10319274B2
- Status: Granted
- Kind: B2
- Application number: 15/762,337
- Filed: 2017-10-12
- Published: 2019-03-07
- Granted: 2019-06-11
- Earliest claimed: 2017-03-10
- Assignees: Boe Technology Group Co., Ltd.; Ordos Yuansheng Optoelectronics Co., Ltd.
- Applicants: Boe Technology Group Co., Ltd.; Ordos Yuansheng Optoelectronics Co., Ltd.
- Inventors: Fei Huang; Jian Sun; Zhen Wang; Wenwen Qin; Xiaozhou Zhan
- Web page: https://patentgrep.com/patent/US10319274B2

## CPC

- G09G 3/20: for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix {no fixed position being assigned to or needed to be assigned to the individual characters or partial characters}
- G09G 3/3266: Details of drivers for scan electrodes
- G09G 3/3666: {with the matrix divided into sections}
- G11C 19/28: using semiconductor elements (G11C19/14, G11C19/36 take precedence)
- G09G 2300/0408: Integration of the drivers onto the display substrate
- G09G 2310/0245: Clearing or presetting the whole screen independently of waveforms, e.g. on power-on (G09G2310/063 takes precedence)
- G09G 2310/0286: Details of a shift registers arranged for use in a driving circuit
- G09G 2310/06: Details of flat display driving waveforms
- G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00)
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

A shift register unit includes an input circuit, an output circuit, a pull-down control circuit, and a pull-down circuit. The pull-down control circuit is coupled to a first power supply signal terminal, a second power supply signal terminal, a pull-up node, a pull-down node, and a reset signal terminal. The pull-down control circuit is configured to transmit a first power supply signal from the first power supply signal terminal to the pull-down node under a control of the first power supply signal, transmit the first power supply signal from the first power supply signal terminal to the pull-down node under a control of the reset signal, and transmit a second power supply signal from the second power supply signal terminal to the pull-down node under a control of the pull-up node.

## Claims

### Claim 1

A shift register unit comprising:
an input circuit coupled to an input signal terminal, a reset signal terminal, a first control signal terminal, a second control signal terminal, and a pull-up node, the input circuit being configured to control an electric potential of the pull-up node under a control of an input signal from the input signal terminal, a reset signal from the reset signal terminal, a first control signal from the first control signal terminal, and a second control signal from the second control signal terminal;
an output circuit coupled to a first clock signal terminal, the pull-up node, and an output terminal, the output circuit being configured to transmit a first clock signal from the first clock signal terminal to the output terminal under a control of the pull-up node;
a pull-down control circuit coupled to a first power supply signal terminal, a second power supply signal terminal, the pull-up node, a pull-down node, and the reset signal terminal, the pull-down control circuit being configured to:
transmit a first power supply signal from the first power supply signal terminal to the pull-down node under a control of the first power supply signal,
transmit the first power supply signal from the first power supply signal terminal to the pull-down node under a control of the reset signal, and
transmit a second power supply signal from the second power supply signal terminal to the pull-down node under a control of the pull-up node,
wherein the first power supply signal is at a first electric potential, and the second power supply signal is at a second electric potential; and
a pull-down circuit coupled to the pull-down node, the second power supply signal terminal, the pull-up node, and the output terminal, the pull-down circuit being configured to transmit the second power supply signal to the pull-up node and the output terminal under a control of the pull-down node.

### Claim 2 (depends on 1)

The shift register unit according to claim 1, wherein:
the pull-down control circuit includes a first pull-down control sub-circuit, a second pull-down control sub-circuit, a third pull-down control sub-circuit, a fourth pull-down control sub-circuit, a fifth pull-down control sub-circuit, and a sixth pull-down control sub-circuit; and
the input circuit includes a first input sub-circuit and a second input sub-circuit.

### Claim 3 (depends on 1)

The shift register unit according to claim 1, further comprising:
a pre-reset circuit coupled to a pre-reset signal terminal, the second power supply signal terminal, the pull-up node, and the pull-down node, the pre-reset circuit being configured to transmit the second power supply signal to the pull-up node and the pre-reset signal to the pull-down node, under a control of a pre-reset signal from the pre-reset signal terminal.

### Claim 4 (depends on 2)

The shift register unit according to claim 2, wherein the first pull-down control sub-circuit includes:
a first transistor, a gate electrode and a first electrode of the first transistor being coupled to the first power supply signal terminal;
a second transistor, a gate electrode of the second transistor being coupled to the first power supply signal terminal, a first electrode of the second transistor being coupled to a second electrode of the first transistor, and a second electrode of the second transistor being coupled to the pull-down node; and
a third transistor, a gate electrode of the third transistor being coupled to the pull-up node, a first electrode of the third transistor being coupled to the second power supply signal terminal, and a second electrode of the third transistor being coupled to the pull-down node.

### Claim 5 (depends on 4)

The shift register unit according to claim 4, wherein:
the pull-down control circuit is further coupled to a second clock signal terminal and the output terminal,
the second pull-down control sub-circuit includes a fourth transistor, a gate electrode and a first electrode of the fourth transistor being coupled to the second clock signal terminal, and a second electrode of the fourth transistor being coupled to the pull-down node,
the fifth pull-down control sub-circuit includes a fifth transistor, a gate electrode of the fifth transistor being coupled to the output terminal, a first electrode of the fifth transistor being coupled to the second power supply signal terminal, and a second electrode of the fifth transistor being coupled to the pull-down node,
the fourth pull-down control sub-circuit includes a sixth transistor, a gate electrode of the sixth transistor being coupled to the pull-up node, a first electrode of the sixth transistor being coupled to the second power supply signal terminal, and a second electrode of the sixth transistor being coupled to the pull-down node, and
the sixth pull-down control sub-circuit includes a first capacitor, a first end of the first capacitor being coupled to the second power supply signal terminal, and a second end of the first capacitor being coupled to the pull-down node.

### Claim 6 (depends on 3)

The shift register unit according to claim 3, wherein the pre-reset circuit includes:
a seventh transistor, a gate electrode of the seventh transistor being coupled to the pre-reset signal terminal, a first electrode of the seventh transistor being coupled to the second power supply signal terminal, and a second electrode of the seventh transistor being coupled to the pull-up node; and
an eighth transistor, a gate electrode and a first electrode of the eighth transistor being coupled to the pre-reset signal terminal, and a second electrode of the eighth transistor being coupled to the pull-down node.

### Claim 7 (depends on 2)

The shift register unit according to claim 2, wherein the first input sub-circuit includes:
a ninth transistor, a gate electrode of the ninth transistor being coupled to the input signal terminal, a first electrode of the ninth transistor being coupled to the first control signal terminal, and a second electrode of the ninth transistor being coupled to the pull-up node; and
a tenth transistor, a gate electrode of the tenth transistor being coupled to the reset signal terminal, a first electrode of the tenth transistor being coupled to the second control signal terminal, and a second electrode of the tenth transistor being coupled to the pull-up node.

### Claim 8 (depends on 2)

The shift register unit according to claim 2, wherein:
the third pull-down control sub-circuit includes an eleventh transistor,
a gate electrode of the eleventh transistor being coupled to the reset signal terminal, a first electrode of the eleventh transistor being coupled to the first power supply signal terminal, and a second electrode of the eleventh transistor being coupled to the pull-down node.

### Claim 9 (depends on 7)

The shift register unit according to claim 7, wherein:
the input circuit is further coupled to the first power supply signal terminal; and
the second input sub-circuit includes a twelfth transistor, a gate electrode of the twelfth transistor being coupled to the first power supply signal terminal, a first electrode of the twelfth transistor being coupled to the second electrode of the ninth transistor and the second electrode of the tenth transistor, and a second electrode of the twelfth transistor being coupled to the pull-up node.

### Claim 10 (depends on 1)

The shift register unit according to claim 1, wherein the output circuit includes:
a thirteenth transistor, a gate electrode of the thirteenth transistor being coupled to the pull-up node, a first electrode of the thirteenth transistor being coupled to the first clock signal terminal;
a fourteenth transistor, a gate electrode of the fourteenth transistor being coupled to the pull-up node, a first electrode of the fourteenth transistor being coupled to a second electrode of the thirteenth transistor, and a second electrode of the fourteenth transistor being coupled to the output terminal; and
a second capacitor, a first end of the second capacitor being coupled to the pull-up node, and a second end of the second capacitor being coupled to the output terminal.

### Claim 11 (depends on 10)

The shift register unit according to claim 10, wherein the output circuit further includes:
a third capacitor, a first end of the third capacitor being coupled to the second power supply signal terminal, and a second end of the third capacitor being coupled to the pull-up node.

### Claim 12 (depends on 1)

The shift register unit according to claim 1, wherein the pull-down circuit includes:
a fifteenth transistor, a gate electrode of the fifteenth transistor being coupled to the pull-down node, a first electrode of the fifteenth transistor being coupled to the second power supply signal terminal, and a second electrode of the fifteenth transistor being coupled to the pull-up node; and
a sixteenth transistor, a gate electrode of the sixteenth transistor being coupled to the pull-down node, a first electrode of the fifteenth transistor being coupled to the second power supply signal terminal, and a second electrode of the fifteenth transistor being coupled to the output terminal.

### Claim 13 (depends on 4)

The shift register unit according to claim 4, wherein:
the transistors are N-type transistors, and
the first electric potential is higher than the second electric potential.

### Claim 14 (depends on 4)

The shift register unit according to claim 4, wherein:
the transistors are P-type transistors, and
the first electric potential is lower than the second electric potential.

### Claim 15

A method for driving a shift register unit, comprising:
providing an input signal at an input signal terminal to cause an input circuit to transmit a first control signal from a first control signal terminal to a pull-up node, the input signal and the first control signal being at a first electric potential;
providing a first clock signal at a first clock signal terminal and holding the pull-up node at the first electric potential, to cause an output circuit to transmit the first clock signal from the first clock signal terminal to an output terminal, the first clock signal being at the first electric potential;
providing a reset signal at a reset signal terminal to cause the input circuit to transmit a second control signal from a second control signal terminal to the pull-up node and to cause a pull-down control circuit to transmit a first power supply signal from a first power supply signal terminal to a pull-down node, the reset signal being at the first electric potential and the second control signal being at a second electric potential; and
providing the first power supply signal at a first power supply signal terminal to cause the pull-down control circuit to transmit the first power supply signal to the pull-down node, and to cause a pull-down circuit to transmit a second power supply signal from a second power supply signal terminal to the pull-up node and the output terminal, the first power supply signal being at the first electric potential and the second power supply signal being at the second electric potential.

### Claim 16 (depends on 15)

The method according to claim 15, further comprising:
providing a pre-reset signal at a pre-reset signal terminal to cause a pre-reset circuit to transmit the second power supply signal to the pull-up node and to transmit the pre-reset signal to the pull-down node, and to cause the pull-down circuit to transmit the second power supply signal to the pull-up node and the output terminal.

### Claim 17 (depends on 15)

The method according to claim 15, wherein:
the first electric potential is higher than the second electric potential.

### Claim 18 (depends on 15)

The method according to claim 15, wherein:
the first electric potential is lower than the second electric potential.

### Claim 19 (depends on 1)

A gate driving circuit, comprising at least two cascaded shift register units according to claim 1.

### Claim 20 (depends on 19)

A display device, comprising the gate driving circuit according to claim 19.