# US 10,319,070 B2 · Dynamic page sizing of page table entries

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- Number: US 10,319,070 B2
- Document ID: US10319070B2
- Status: Granted
- Kind: B2
- Application number: 16/120,591
- Filed: 2018-09-04
- Published: 2019-01-24
- Granted: 2019-06-11
- Earliest claimed: 2017-04-10
- Assignees: Intel Corporation
- Applicants: Intel Corporation
- Inventors: Abhishek R. Appu; Joydeep Ray; Altug Koker; Balaji Vembu; Prasoonkumar P. Surti; Kamal Sinha; Vasanth Ranganathan; Kiran C. Veernapu; Bhushan M. Borole; Wenyin Fu
- Web page: https://patentgrep.com/patent/US10319070B2

## CPC

- G06T 1/60: Memory management
- G06T 1/20: Processor architectures; Processor configuration, e.g. pipelining
- G06T 15/005: {General purpose rendering architectures}
- G06T: IMAGE DATA PROCESSING OR GENERATION, IN GENERAL

## Abstract

In accordance with one embodiment each page table entry maps a variable page size (per entry), if multiple continuous virtual pages map to contiguous physical pages. This may drastically reduce the number of translation lookaside buffer (TLB) entries needed since each entry can potentially map a larger chunk of memory, in some embodiments.

## Claims

### Claim 1

An apparatus comprising:
a graphics processor;
a graphics driver to receive a memory block allocation and, in response to said allocation, to set a page table entry to indicate a variable page table block size to match a size of the allocation; and
a memory coupled to said processor.

### Claim 2 (depends on 1)

The apparatus of claim 1, said graphics driver to set the page table entry to indicate the block size.

### Claim 3 (depends on 1)

The apparatus of claim 1, said graphics driver to use a base memory unit size and to specify a multiple of said size as the variable page table block size in a page table entry.

### Claim 4 (depends on 3)

The apparatus of claim 3 wherein said base memory unit size is 4 KB.

### Claim 5 (depends on 1)

The apparatus of claim 1 wherein said graphics driver to dynamically indicate said page table block size in multiples of 4 KB.

### Claim 6 (depends on 1)

The apparatus of claim 1, said graphics driver to dynamically indicate one of at least four selectable variable page table block sizes.

### Claim 7 (depends on 1)

The apparatus of claim 1, said graphics driver to indicate the page table block size at a size other than 4 KB, 64 KB, or 2 MB.

### Claim 8 (depends on 1)

The apparatus of claim 1, said graphics driver to indicate the page table entry size to reduce the number of translation lookaside buffer entries.

### Claim 9

A system comprising:
a graphics processor;
a graphics driver to receive a memory block allocation and, in response to said allocation, to set a page table entry to indicate a variable page table block size to match a size of the allocation;
a memory coupled to said graphics processor; and
a central processing unit to provide said memory block allocation to said graphics driver.

### Claim 10 (depends on 9)

The system of claim 9, said graphics driver to set the page table entry to indicate the block size.

### Claim 11 (depends on 9)

The system of claim 9, said graphics driver to use a base memory unit size and to specify a multiple of said size as the variable page table block size in a page table entry.

### Claim 12 (depends on 11)

The system of claim 11 wherein said base memory unit size is 4 KB.

### Claim 13 (depends on 9)

The system of claim 9 wherein said graphics driver to dynamically indicate said page table block size in multiples of 4 KB.

### Claim 14 (depends on 9)

The system of claim 9, said graphics driver to dynamically indicate one of at least four selectable variable page table block sizes.

### Claim 15 (depends on 9)

The system of claim 9, said graphics driver to indicate the page table block size at a size other than 4 KB, 64 KB, or 2 MB.

### Claim 16 (depends on 9)

The system of claim 9, said graphics driver to indicate the page table entry size to reduce the number of translation lookaside buffer entries.

### Claim 17

One or more non-transitory computer readable media storing instructions to perform a sequence comprising:
receiving a request for a page table size based on a size of memory block allocation; and
in response to said allocation, setting a page table entry to indicate a variable page table block size to match the allocation size.

### Claim 18 (depends on 17)

The media of claim 17, said media storing instructions to perform a sequence including setting the page table entry to indicate that allocation size.

### Claim 19 (depends on 17)

The media of claim 17, said media storing instructions to perform a sequence including using a base memory unit size and to specify a multiple of said size as the variable page table block size in a page table entry.

### Claim 20 (depends on 19)

The media of claim 19, said media storing instructions to perform a sequence further storing instructions to perform a sequence wherein said base memory unit size is 4 KB.

### Claim 21 (depends on 17)

The media of claim 17, said media storing instructions to perform a sequence including dynamically setting said page table block size in multiples of 4 KB.

### Claim 22 (depends on 17)

The media of claim 17, said media storing instructions to perform a sequence including dynamically setting one of at least four selectable variable page table block sizes.

### Claim 23 (depends on 17)

The media of claim 17, said media storing instructions to perform a sequence including setting the page table block size at a size other than 4 KB, 64 KB, or 2 MB.

### Claim 24 (depends on 17)

The media of claim 17, said media storing instructions to perform a sequence including setting the page table entry size to reduce the number of translation lookaside buffer entries.