Printed wiring board

A printed wiring board, comprising:

• a core substrate;
• a first build-up layer formed on a first surface side of the core substrate;
• and
• a second build-up layer formed on a second surface side of the core substrate on an opposite side with respect to the first surface side,
• wherein the core substrate includes a core layer having a plurality of through holes, a plurality of through-hole conductors formed in the plurality of through holes respectively such that each of the through holes has a first opening tapering from a first surface of the core layer toward a second surface of the core layer on an opposite side with respect to the first surface, and a second opening tapering from the second surface of the core layer toward the first surface of the core layer, a plurality of first through-hole lands formed on the first surface of the core layer such that the first through-hole lands are directly connected to the through-hole conductors respectively, and a plurality of second through-hole lands formed on the second surface of the core layer such that the second through-hole lands are directly connected to the through-hole conductors respectively, the first build-up layer includes a first resin insulating layer, a plurality of first via conductors penetrating through the first resin insulating layer and connecting to the first through-hole lands respectively, a plurality of first via lands formed on the first resin insulating layer and directly connected to the first via conductors respectively, an outermost first resin insulating layer formed on the first resin insulating layer, an outermost first conductor layer formed on the outermost first resin insulating layer, and a plurality of outermost first via conductors penetrating through the outermost first resin insulating layer and electrically connecting to the first via conductors respectively, the second build-up layer includes a second resin insulating layer, a plurality of second via conductors penetrating through the second resin insulating layer and connecting to the second through-hole lands respectively, a plurality of second via lands formed on the second resin insulating layer and directly connected to the second via conductors respectively, an outermost second resin insulating layer formed on the second resin insulating layer, an outermost second conductor layer formed on the outermost second resin insulating layer, and a plurality of outermost second via conductors penetrating through the outermost second resin insulating layer and electrically connecting to the second via conductors respectively, the through-hole conductors, first through-hole lands and second through-hole lands form a plurality of through-hole structures such that each of the through-hole conductors has a joining area at an intersection between the first opening and the second opening, each of the first through-hole lands, second through-hole lands, first via lands, second via lands, outermost first conductor layer and outermost second conductor layer comprises a metal foil, a seed layer formed on the metal foil, and an electrolytic plating film formed on the seed layer, and the metal foil of the first via lands has a mat surface at the first surface of the core layer, the metal foil of the second via lands has a mat surface on the second surface of the core layer, the metal foil of the first via lands has a mat surface on the first resin insulating layer, the metal foil of the second via lands has a mat surface on the second resin insulating layer, the metal foil of the outermost first conductor layer has a mat surface on the outermost first resin insulating layer, the metal foil of the second conductor layer has a mat surface on the outermost second resin insulating layer such that the mat surface of the first via lands has a ten-point average roughness RzI1 of an unevenness that is smaller than ten-point average roughness Rz1, Rz2, RzO1, RzO2 of an unevenness of the mat surfaces of the first through-hole lands, second through-hole lands, outermost first conductor layer, and outermost second conductor layer, and that the mat surface of the second via lands has a ten-point average roughness RzI2 of an unevenness that is smaller than ten-point average roughness Rz1, Rz2, RzO1, RzO2 of an unevenness of the mat surfaces of the first through-hole lands, second through-hole lands, outermost first conductor layer, and outermost second conductor layer.