# US 10,313,678 B2 · Image signal processing apparatus and display device having the same

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- Number: US 10,313,678 B2
- Document ID: US10313678B2
- Status: Granted
- Kind: B2
- Application number: 15/861,478
- Filed: 2018-01-03
- Published: 2019-01-10
- Granted: 2019-06-04
- Earliest claimed: 2017-07-06
- Assignees: Samsung Display Co., Ltd.
- Applicants: Samsung Display Co., Ltd.
- Inventors: Masahiko Takiguchi
- Web page: https://patentgrep.com/patent/US10313678B2

## CPC

- H04N 19/172: the region being a picture, frame or field
- H04N 19/117: Filters, e.g. for pre-processing or post-processing (sub-band filter banks H04N19/635)
- H04N 19/136: Incoming video signal characteristics or properties
- H04N 19/182: the unit being a pixel
- H04N 19/184: the unit being bits, e.g. of the compressed video stream
- G09G 2320/02: Improving the quality of display appearance
- H04N: PICTORIAL COMMUNICATION, e.g. TELEVISION
- G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00)

## Abstract

An image signal processing apparatus includes an adder to add an input data signal of a present frame to a cumulative data signal of a previous frame to output a cumulative data signal, an analyzing block to analyze a processing range of the cumulative data signal, a processing block to process the cumulative data signal based on the processing range to output a processed data signal, an encoding block to compress the processed data signal to output an encoded data signal, a memory to store the encoded data signal and the processing range, a decoding block to decode the encoded data signal read out from the memory to output a decoded data signal, and an inverse processing block to inversely process the decoded data signal based on the processing range to output an output data signal.

## Claims

### Claim 1

An image signal processing apparatus comprising:
an adder to add an input data signal of a present frame to a cumulative data signal of a previous frame to output a cumulative data signal;
an analyzing block to analyze a processing range of the cumulative data signal;
a processing block to process the cumulative data signal based on the processing range to output a processed data signal;
an encoding block to compress the processed data signal to output an encoded data signal;
a memory to store the encoded data signal and the processing range;
a decoding block to decode the encoded data signal read out from the memory to output a decoded data signal; and
an inverse processing block to inversely process the decoded data signal based on the processing range to output an output data signal, wherein the output data signal is provided to the adder as the cumulative data signal of the previous frame.

### Claim 2 (depends on 1)

The image signal processing apparatus of claim 1, wherein the processing range comprises a valid most significant bit of the cumulative data signal.

### Claim 3 (depends on 2)

The image signal processing apparatus of claim 2, wherein the analyzing block is to detect the valid most significant bit of the cumulative data signal at every frame.

### Claim 4 (depends on 2)

The image signal processing apparatus of claim 2, wherein the analyzing block is to detect the valid most significant bit of the cumulative data signal at every set frame.

### Claim 5 (depends on 2)

The image signal processing apparatus of claim 2, wherein the processing block is to bit-shift the cumulative data signal in a first direction based on the valid most significant bit to output the processed data signal.

### Claim 6 (depends on 5)

The image signal processing apparatus of claim 5, wherein the processing block is to determine a number of bits, which is used to bit-shift the cumulative data signal in the first direction, depending on a difference between the number of bits of the cumulative data signal and the valid most significant bit.

### Claim 7 (depends on 5)

The image signal processing apparatus of claim 5, wherein the encoding block is to delete a lower k bits (k is a positive integer) of the processed data signal to output the encoded data signal.

### Claim 8 (depends on 7)

The image signal processing apparatus of claim 7, wherein the decoding block is to allow the lower k bits of the encoded data signal to be filled with 0s to output the decoded data signal.

### Claim 9 (depends on 5)

The image signal processing apparatus of claim 5, wherein the inverse processing block is to bit-shift the decoded data signal in a second direction opposite to the first direction to output the output data signal.

### Claim 10 (depends on 2)

The image signal processing apparatus of claim 2, wherein the processing block is to delete a portion of a data signal corresponding to a second pixel among first and second pixels when the valid most significant bit of the cumulative data signal is equal to or greater than a first critical value.

### Claim 11 (depends on 2)

The image signal processing apparatus of claim 2, wherein the processing block is to delete a whole portion of a data signal corresponding to a second pixel among first and second pixels when the valid most significant bit of the cumulative data signal is equal to or greater than a second critical value.

### Claim 12

A display device comprising:
a display panel comprising a plurality of pixels;
a power supply to provide a first power voltage and a second power voltage to the display panel; and
a driving circuit to receive an input data signal and to provide an image data signal to the pixels such that an image is displayed through the pixels, the driving circuit comprising an image signal processing apparatus to cumulate the image data signal provided to the pixels, the image signal processing apparatus comprising:
an adder to add the input data signal of a present frame to a cumulative data signal of a previous frame to output a cumulative data signal;
an analyzing block to analyze a processing range of the cumulative data signal;
a processing block to process the cumulative data signal based on the processing range to output a processed data signal;
an encoding block to compress the processed data signal to output an encoded data signal;
a memory to store the encoded data signal and the processing range;
a decoding block to decode the encoded data signal read out from the memory to output a decoded data signal; and
an inverse processing block to inversely process the decoded data signal based on the processing range to output an output data signal, wherein the output data signal is provided to the adder as the cumulative data signal of the previous frame.

### Claim 13 (depends on 12)

The display device of claim 12, wherein the processing range comprises a valid most significant bit of the cumulative data signal.

### Claim 14 (depends on 13)

The display device of claim 13, wherein the processing block is configured to bit-shift the cumulative data signal in a first direction based on the valid most significant bit to output the processed data signal.

### Claim 15 (depends on 14)

The display device of claim 14, wherein the inverse processing block is to bit-shift the decoded data signal in a second direction opposite to the first direction to output the output data signal.

### Claim 16 (depends on 13)

The display device of claim 13, wherein the encoding block is to delete a lower k bits (k is a positive integer) of the processed data signal to output the encoded data signal.

### Claim 17 (depends on 16)

The display device of claim 16, wherein the decoding block is to allow the lower k bits of the encoded data signal to be filled with 0s to output the decoded data signal.

### Claim 18 (depends on 13)

The display device of claim 13, wherein the processing block is to delete a portion of a data signal corresponding to a second pixel among first and second pixels when the valid most significant bit of the cumulative data signal is equal to or greater than a first critical value.

### Claim 19

A method of operating an image signal processing apparatus, the method comprising:
adding an input data signal of a present frame to a cumulative data signal of a previous frame;
analyzing a processing range of the cumulative data signal;
processing the cumulative data signal based on the processing range to output a processed data signal;
compressing the processed data signal to output an encoded data signal;
decoding the encoded data signal to output a decoded data signal; and
inversely processing the decoded data signal based on the processing range to output an output data signal.

### Claim 20 (depends on 19)

The method of claim 19, wherein the processing range comprises a valid most significant bit of the cumulative data signal.