# US 10,313,641 B2 · Shift register with reduced wiring complexity > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,313,641 B2 - Document ID: US10313641B2 - Status: Granted - Kind: B2 - Application number: 15/352,260 - Filed: 2016-11-15 - Published: 2017-06-08 - Granted: 2019-06-04 - Earliest claimed: 2015-12-04 - Assignees: Google Inc. - Applicants: Google LLC - Inventors: Jason Rupert Redgrave - Web page: https://patentgrep.com/patent/US10313641B2 ## CPC - G11C 19/38: two-dimensional [2D], e.g. horizontal and vertical shift registers - G06F 15/173: using an interconnection network, e.g. matrix, shuffle, pyramid, star, snowflake - G06F 15/8015: {One dimensional arrays, e.g. rings, linear arrays, buses} - G06T 1/20: Processor architectures; Processor configuration, e.g. pipelining - G11C 7/1075: {for multiport memories each having random access ports and serial ports, e.g. video RAM} - G11C 19/00: Digital stores in which the information is moved stepwise, e.g. shift registers - H01P 5/12: Coupling devices having more than two ports (H01P5/04 takes precedence) - H03K 19/17744: {for input/output signals} - H04N 5/907: using static stores, e.g. storage tubes or semiconductor memories (H04N5/91 takes precedence) - G11C 19/28: using semiconductor elements (G11C19/14, G11C19/36 take precedence) - G11C: STATIC STORES (semiconductor memory devices H10B) - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - G06T: IMAGE DATA PROCESSING OR GENERATION, IN GENERAL - H01P: WAVEGUIDES; RESONATORS, LINES, OR OTHER DEVICES OF THE WAVEGUIDE TYPE (operating at optical frequencies G02B) - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) - H04N: PICTORIAL COMMUNICATION, e.g. TELEVISION ## Abstract A shift register is described. The shift register includes a plurality of cells and register space. The shift register includes circuitry having inputs to receive shifted data and outputs to transmit shifted data, wherein: i) circuitry of cells physically located between first and second logically ordered cells are configured to not perform any logical shift; ii) circuitry of cells coupled to receive shifted data transmitted by an immediately preceding logically ordered cell comprises circuitry for writing into local register space data received at an input assigned an amount of shift specified in a shift command being executed by the shift register, and, iii) circuitry of cells coupled to transmit shifted data to an immediately following logically ordered cell comprises circuitry to transmit data from an output assigned an incremented shift amount from a shift amount of an input that the data was received on. ## Claims ### Claim 1 A device comprising a plurality of shifting unit cells that are physically arranged out of logical order, each shifting unit cell comprising local register space and circuitry having inputs configured to receive shifted data and outputs configured to transmit shifted data, wherein each of the inputs is assigned a different respective shift amount and each of the outputs is assigned a different respective shift amount, wherein the circuitry of each shifting unit cell comprises: (i) first circuitry configured to receive data from a preceding logically ordered shifting unit cell at a respective input assigned to a respective shift amount specified in a shift command and to write the received data into the local register space of the shifting unit cell, and (ii) second circuitry configured to transmit data to a following logically ordered cell from a respective output assigned to an incremented shift amount from a shift amount of an input at which the data was received. ### Claim 2 (depends on 1) The device of claim 1, wherein the second circuitry further comprises circuitry configured to read data from the local register space of the shifting unit cell and to transmit the data from an output assigned to a shift amount of 1. ### Claim 3 (depends on 1) The device of claim 1, wherein the shifting unit cells are configured to propagate data in a closed loop. ### Claim 4 (depends on 3) The device of claim 3, wherein the shifting unit cells are physically arranged such that shifts occur either in a first direction or in a second direction along the closed loop. ### Claim 5 (depends on 1) The device of claim 1, wherein each shifting unit cell is part of a bi-directional shift register. ### Claim 6 (depends on 1) The device of claim 1, wherein the plurality of shifting unit cells form a two-dimensional shift register array. ### Claim 7 (depends on 1) The device of claim 1, further comprising: for each shifting unit cell, a non-shifting unit cell, each non-shifting unit cell having inputs to receive shifted data and corresponding outputs that transmit the received shifted data without shifting it further, wherein each of the inputs is assigned a different respective shift amount. ### Claim 8 A two-dimensional shift register array comprising a plurality of rows and columns of shifting unit cells, wherein the shifting unit cells in a particular row or column are physically arranged out of logical order, each shifting unit cell comprising local register space and circuitry having inputs configured to receive shifted data and outputs configured to transmit shifted data, wherein each of the inputs is assigned a different respective shift amount and each of the outputs is assigned a different respective shift amount, wherein the circuitry of each shifting unit cell comprises: (i) first circuitry configured to receive data from a preceding logically ordered shifting unit cell at a respective input assigned to a respective shift amount specified in a shift command and to write the received data into the local register space of the shifting unit cell, and (ii) second circuitry configured to transmit data to a following logically ordered cell from a respective output assigned to an incremented shift amount from a shift amount of an input at which the data was received. ### Claim 9 (depends on 8) The two-dimensional shift-register array of claim 8, wherein the second circuitry further comprises circuitry configured to read data from the local register space of the shifting unit cell and to transmit the data from an output assigned to a shift amount of 1. ### Claim 10 (depends on 8) The two-dimensional shift-register array of claim 8, wherein the shifting unit cells are configured to propagate data in a closed loop. ### Claim 11 (depends on 10) The two-dimensional shift-register array of claim 10, wherein the shifting unit cells are physically arranged such that shifts occur either in a first direction or in a second direction along the closed loop. ### Claim 12 (depends on 8) The two-dimensional shift-register array of claim 8, wherein each shifting unit cell is part of a bi-directional shift register. ### Claim 13 (depends on 8) The two-dimensional shift-register array of claim 8, wherein the two-dimensional shift-register array is within a computing system having one or more processing cores coupled to a system memory. ### Claim 14 (depends on 8) The two-dimensional shift-register array of claim 8, further comprising: for each shifting unit cell, a non-shifting unit cell, each non-shifting unit cell having inputs to receive shifted data and corresponding outputs that transmit the received shifted data without shifting it further, wherein each of the inputs is assigned a different respective shift amount. ### Claim 15 An image processor comprising: a two-dimensional execution lane array; and a two-dimensional shift-register array comprising a plurality of rows and columns of shifting unit cells, wherein the shifting unit cells in a particular row or column are physically arranged out of logical order, each shifting unit cell comprising local register space and circuitry having inputs configured to receive shifted data and outputs configured to transmit shifted data, wherein each of the inputs is assigned a different respective shift amount and each of the outputs is assigned a different respective shift amount, wherein the circuitry of each shifting unit cell comprises: (i) first circuitry configured to receive data from a preceding logically ordered shifting unit cell at a respective input assigned to a respective shift amount specified in a shift command and to write the received data into the local register space of the shifting unit cell, and (ii) second circuitry configured to transmit data to a following logically ordered cell from a respective output assigned to an incremented shift amount from a shift amount of an input at which the data was received. ### Claim 16 (depends on 15) The image processor of claim 15, wherein the second circuitry further comprises circuitry configured to read data from the local register space of the shifting unit cell and to transmit the data from an output assigned to a shift amount of 1. ### Claim 17 (depends on 15) The image processor of claim 15, wherein the shifting unit cells are configured to propagate data in a closed loop. ### Claim 18 (depends on 17) The image processor of claim 17, wherein the shifting unit cells are physically arranged such that shifts occur either in a first direction or in a second direction along the closed loop. ### Claim 19 (depends on 15) The image processor of claim 15, further comprising: for each shifting unit cell, a non-shifting unit cell, each non-shifting unit cell having inputs to receive shifted data and corresponding outputs that transmit the received shifted data without shifting it further, wherein each of the inputs is assigned a different respective shift amount.