# US 10,313,620 B2 · Image data output device for image signal processor > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,313,620 B2 - Document ID: US10313620B2 - Status: Granted - Kind: B2 - Application number: 15/100,501 - Filed: 2014-11-11 - Published: 2016-10-13 - Granted: 2019-06-04 - Earliest claimed: 2013-11-29 - Assignees: SK hynix Inc. - Applicants: SK hynix Inc. - Inventors: Sang Wook Ahn; Yong Woon Lee; Huy Chan Jung; Heui-Gyun Ahn - Web page: https://patentgrep.com/patent/US10313620B2 ## CPC - H04N 25/40: Extracting pixel data from image sensors by controlling scanning circuits, e.g. by modifying the number of pixels sampled or to be sampled - H04N 25/77: Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components - H04N 25/771: comprising storage means other than floating diffusion - H04N 25/7795: {Circuitry for generating timing or clock signals} - H04N 25/78: Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters - H04N 25/531: by controlling rolling shutters in CMOS SSIS - H04N: PICTORIAL COMMUNICATION, e.g. TELEVISION ## Abstract The present invention relates to a technology with enables an image signal processor to output image data at a faster speed while using a memory having a smaller capacity. The image signal processor includes a pair of line memories for storing image data output from an analog-digital converter such that the image data alternates in units of horizontal lines, and outputting the stored image data in units of blocks according to a first-in-first-out method. ## Claims ### Claim 1 An image data output device for an image signal processor that dividing and outputting image data of each horizontal line or each vertical line by a plurality of blocks when image data, which are outputted from a pixel array having a plurality of unit pixel for an image sensing, are stored in an external device, comprising: a decoder suitable for decoding and outputting image signals, which are sequentially outputted from the pixel array; an analog-digital converter suitable for sequentially converting decoded analog image signals provided from the decoder into digital signals; a pair of line memories suitable for alternately storing image data, which are outputted from the analog-digital converter, by the each horizontal line on a basis of the pixel array, outputting the image data using a first-in-first-out method, and outputting the image data by a block unit, wherein a first line memory of the pair of line memories includes whole memories corresponding to whole pixels of a first horizontal line of the pixel array and a second line memory of the pair of line memories includes whole memories corresponding to whole pixels of a second horizontal line of the pixel array; and a multiplexer suitable for sequentially selecting and outputting the image data, which are outputted from the pair of line memories by the block unit. ### Claim 2 (depends on 1) The image data output device for the image signal processor of claim 1, wherein the pixel array operates using a rolling shutter manner or a global shutter manner. ### Claim 3 (depends on 1) The image data output device for the image signal processor of claim 1, wherein the pixel array is manufactured as a semiconductor chip of an independent type through a manufacturing process of an image sensor exclusive use. ### Claim 4 (depends on 1) The image data output device for the image signal processor of claim 1, wherein the decoder decodes and outputs the image signals using a sensing timing signal provided from a sensing timing signal processor. ### Claim 5 (depends on 1) The image data output device for the image signal processor of claim 1, wherein the decoder is one of a row decoder for decoding and outputting the image signals of a horizontal line, which are sequentially outputted from the pixel array, and a column decoder for decoding and outputting the image signals of a vertical line, which are sequentially outputted from the pixel array. ### Claim 6 (depends on 1) The image data output device for the image signal processor of claim 1, wherein the analog-digital converter simultaneously converts the image signals of analog for an entire pixel of one row provided from the decoder into digital signals, or converts the image signals of analog by a pixel unit. ### Claim 7 (depends on 1) The image data output device for the image signal processor of claim 1, wherein the analog-digital convert simultaneously converts the image signals of analog for an entire pixel of one column provided from the decoder into digital signals, or converts the image signals of analog by a pixel unit. ### Claim 8 (depends on 1) The image data output device for the image signal processor of claim 1, wherein the pair of line memories include a structure having a variable capacity. ### Claim 9 (depends on 1) The image data output device for the image signal processor of claim 1, wherein the pair of line memories include a plurality of pair of line memories. ### Claim 10 (depends on 1) The image data output device for the image signal processor of claim 1, wherein the pair of line memories are manufactured as a semiconductor chip of an independent type through a manufacturing process of a logic exclusive use. ### Claim 11 (depends on 1) The image data output device for the image signal processor of claim 1, wherein the pair of line memories include a signal processing buffer function for improving a quality of the outputted image data. ### Claim 12 (depends on 1) The image data output device for the image signal processor of claim 1, wherein the multiplexer includes an image signal processor for performing a compensation that prevents a pixel interference, a shading compensation that compensates a color sensitivity difference, or a noise cancelling when the image data are outputted by the block unit. ### Claim 13 (depends on 12) The image data output device for the image signal processor of claim 12, wherein the image signal processor is manufactured as a semiconductor chip of an independent type through a manufacturing process of a logic exclusive use.