# US 10,313,432 B2 · Multi-microcontroller system, internet of things gateway system, and control flow of multi-microcontroller system based on network bridge

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- Number: US 10,313,432 B2
- Document ID: US10313432B2
- Status: Granted
- Kind: B2
- Application number: 15/385,312
- Filed: 2016-12-20
- Published: 2018-06-21
- Granted: 2019-06-04
- Earliest claimed: 2016-12-20
- Assignees: National Central University
- Applicants: National Central University
- Inventors: Ching-Han Chen; Jhong-Ci Liou
- Web page: https://patentgrep.com/patent/US10313432B2

## CPC

- H04W 4/70: Services for machine-to-machine communication [M2M] or machine type communication [MTC]
- H04L 12/66: Arrangements for connecting between networks having differing types of switching systems, e.g. gateways
- H04L 67/1001: for accessing one among a plurality of replicated servers
- H04L 67/12: specially adapted for proprietary or special-purpose networking environments, e.g. medical networks, sensor networks, networks in vehicles or remote metering networks
- H04W: WIRELESS COMMUNICATION NETWORKS (broadcast communication H04H; communication systems using wireless links for non-selective communication, e.g. wireless extensions H04M1/72)
- H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M)

## Abstract

A multi-microcontroller system, comprising a master microcontroller and a plurality of slave microcontrollers; wherein the master microcontroller is connected with the slave microcontrollers respectively via a network bridge; the network bridge forms a first communication part with a first memory interface and a first SPI interface, the plurality of first communication parts are connected with the master microcontroller and the slave microcontrollers, respectively; the network bridge is primarily responsible for processing transmission of control signals and data between the master microcontroller and the slave microcontrollers, and serves as a temporary storage area for common memory such that the states of the slave microcontrollers are put under automated management, the addresses of the slave microcontrollers are designated, and memory blocks are allocated.

## Claims

### Claim 1

A multi-microcontroller system, comprising:
a master microcontroller and a plurality of slave microcontrollers;
wherein the master microcontroller is connected with the plurality of slave microcontrollers respectively via a network bridge;
the network bridge forms a first communication part with a first memory interface and a first SPI interface, a plurality of first communication parts are connected with the master microcontroller and the plurality of slave microcontrollers, respectively;
the network bridge is primarily responsible for processing transmission of control signals and data between the master microcontroller and the slave microcontrollers, and serves as a temporary storage area for common memory such that the states of the plurality of slave microcontrollers are put under automated management, the addresses of the plurality of slave microcontrollers are designated, and memory blocks are allocated;
wherein the network bridge further comprises a master controller that is responsible for analyzing a command sent by the master microcontroller and for data transfer between the master microcontroller and the plurality of slave microcontrollers;
wherein the master controller is composed of a microprogram control unit, a datapath unit and a function unit.

### Claim 2 (depends on 1)

The multi-microcontroller system of claim 1, wherein the network bridge can consist of a Field Programmable Gate Array (FPGA) or an Application-Specific Integrated Circuit (ASIC).

### Claim 3 (depends on 2)

The multi-microcontroller system of claim 2, wherein the master microcontroller is connected with the first communication part through a second communication part, and the second communication part comprises a second memory interface and a second SPI interface.

### Claim 4 (depends on 3)

The multi-microcontroller system of claim 3, wherein the plurality of slave microcontrollers are connected with the first communication part through a third communication part, and the third communication part comprises a third memory interface and a third SPI interface.

### Claim 5 (depends on 4)

The multi-microcontroller system of claim 4, wherein the first memory interface, the second memory interface and the third memory interface function as data communication interfaces; and the first SPI interface, the second SPI interface and the third SPI interface function as state control interfaces.

### Claim 6

An Internet of Things gateway system, comprising:
a master microcontroller, a network bridge and a plurality of slave microcontrollers;
wherein the master microcontroller and the network bridge are arranged in a master device, and the plurality of slave microcontrollers are each arranged in a plurality of electronic devices;
the network bridge forms a first communication part with a first memory interface and a first SPI interface;
the master microcontroller is connected with the first communication part through a second communication part, and the second communication part comprises a second memory interface and a second SPI interface;
the plurality of slave microcontrollers are connected with the first communication part through a third communication part, and the third communication part comprises a third memory interface and a third SPI interface;
thus the plurality of electronic devices are managed by the master device via the network bridge;
wherein the network bridge is connected with the second communication part and the third communication part respectively via the first communication part, processes transmission of control signals and data between the master microcontroller and the plurality of slave microcontrollers, and serves as a temporary storage area for common memory such that the states of the plurality of slave microcontrollers are put under automated management, the addresses of the plurality of slave microcontrollers are designated, and memory blocks are allocated.

### Claim 7 (depends on 6)

The Internet of Things gateway system of claim 6, wherein transmission of control signals and data among the first communication part, the second communication part and the third communication part is accomplished by use of ZigBee, Mobile Communications 2G, 3G and 4G, Bluetooth, USB, CAN, VPN, Wi-Fi or MQTT protocols.

### Claim 8 (depends on 6)

The Internet of Things gateway system of claim 6, wherein the network bridge further comprises a master controller that is responsible for analyzing a command sent by the master microcontroller and for data transfer between the master microcontroller and the plurality of slave microcontrollers.

### Claim 9 (depends on 8)

The Internet of Things gateway system of claim 8, wherein the master controller is composed of a microprogram control unit, a datapath unit and a function unit.

### Claim 10 (depends on 6)

The Internet of Things gateway system of claim 6, wherein the electronic device is one of or a mixture of the group consisting of a camera, a sensor, an actuator, a DI/DO or a programmable logic controller (PLC).

### Claim 11

A control flow of a multi-microcontroller system based on a network bridge, the multi-microcontroller system comprising a master microcontroller and a plurality of slave microcontrollers, wherein the master microcontroller is connected with the plurality of slave microcontrollers respectively via a network bridge, the control flow comprises the following steps:
step 1: initializing the master microcontroller, the network bridge and the plurality of slave microcontrollers;
step 2: inquiring the master microcontroller and the plurality of slave microcontrollers and assigning IDs and addresses to the master microcontroller and the plurality of slave microcontrollers by the network bridge;
step 3: returning the number of the plurality of slave microcontrollers to the master microcontroller and then judging whether the master microcontroller sends a command of data retrieval by the network bridge; if so, proceeding with step 4, and if not, returning to step 1;
step 4: analyzing the command sent by the master microcontroller by the network bridge, wherein the command includes a designated ID of one of the plurality of slave microcontrollers and a control command;
step 5: executing the control command on the designated ID of the slave microcontroller; and
step 6: receiving a value returned by the slave microcontroller, and returning to step 1 upon the completion of reception;
wherein a memory interface functions as a data communication interface and an SPI interface functions as a state control interface among the master microcontroller, the network bridge and the slave microcontroller.