# US 10,313,258 B2 · Packet processing method and apparatus

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 10,313,258 B2
- Document ID: US10313258B2
- Status: Granted
- Kind: B2
- Application number: 15/818,162
- Filed: 2017-11-20
- Published: 2018-03-15
- Granted: 2019-06-04
- Earliest claimed: 2015-05-25
- Assignees: Huawei Technologies Co., Ltd.
- Applicants: Huawei Technologies Co., Ltd.
- Inventors: Cong Chen; Zhu Cheng
- Web page: https://patentgrep.com/patent/US10313258B2

## CPC

- H04L 47/56: implementing delay-aware scheduling
- G06F 5/06: for changing the speed of data flow, i.e. speed regularising {or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor (G06F7/78 takes precedence)}
- H04L 12/54: Store-and-forward switching systems (packet switching systems H04L45/00, H04L47/00)
- H04L 43/0858: {One way delays}
- H04J 3/0667: {Bidirectional timestamps, e.g. NTP or PTP for compensation of clock drift and for compensation of propagation delays (arrangements for monitoring round trip delays in packet switching networks H04L43/0864)}
- H04L 47/22: Traffic shaping
- H04L 47/50: Queue scheduling
- H04L 49/901: using storage descriptor, e.g. read or write pointers
- H04W 88/085: {Access point devices with remote components}
- H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M)
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- H04J: MULTIPLEX COMMUNICATION (transmission in general H04B; peculiar to transmission of digital information H04L5/00; systems for the simultaneous or sequential transmission of more than one television signal H04N7/08; in exchanges H04Q11/00; stereophonic systems H04S)
- H04W: WIRELESS COMMUNICATION NETWORKS (broadcast communication H04H; communication systems using wireless links for non-selective communication, e.g. wireless extensions H04M1/72)

## Abstract

Embodiments of the present invention provide a packet processing method and apparatus. After receiving a packet, a first network device processes the packet, and determines a first latency of the processed packet in a FIFO memory, where: the first latency is equal to a difference obtained by subtracting a second latency from a target latency, the second latency includes a third latency, and the third latency includes a time interval for processing the packet.

## Claims

### Claim 1

A method, comprising:
receiving, by a first network device, a packet at a first time;
processing, by the first network device, the packet to obtain a processed packet, and writing the processed packet into a buffer memory;
reading, by the first network device, the processed packet from the buffer memory at a second time;
determining, by the first network device at a time after the second time, a first latency of the processed packet in a first in first out (FIFO) memory, wherein the first latency is equal to a difference obtained by subtracting a second latency from a target latency, the target latency is equal to a period from the first time to a third time at which the processed packet is forwarded by the first network device through an egress port, the second latency is equal to a sum of a third latency and a fourth latency, the third latency is equal to a period from the first time to the second time, the fourth latency is a fixed latency, and the FIFO memory comprises multiple contiguous storage units;
setting, by the first network device, a read pointer and/or a write pointer according to the determined first latency;
writing, by the first network device according to the set write pointer, the processed packet into a storage unit in the FIFO memory, or reading, according to the set read pointer, the processed packet from a storage unit in the FIFO memory; and
forwarding, by the first network device at the third time through the egress port, the processed packet that is read from the FIFO memory.

### Claim 2 (depends on 1)

The method according to claim 1, wherein setting, by the first network device, the write pointer according to the determined first latency comprises:
determining, by the first network device according to the first latency, a location of the storage unit in the FIFO memory; and
setting, by the first network device, the write pointer according to the determined location of the storage unit, wherein the set write pointer points to the storage unit.

### Claim 3 (depends on 2)

The method according to claim 2, wherein determining, by the first network device according to the first latency, a location of the storage unit in the FIFO memory comprises:
determining, by the first network device, the location of the storage unit in the FIFO memory according to the following formula:
P_add
=
⌈
T
1
T
read
⌉
-
1
,
wherein P_add indicates a quantity of storage units between a first storage unit and a second storage unit, wherein the first storage unit and the second storage unit are storage units in the multiple contiguous storage units, the first storage unit is configured to store the processed packet, the multiple contiguous storage units are configured to store a packet queue, each storage unit is configured to store only one packet or null data, and the second storage unit is configured to store a tail of the packet queue; T1 indicates the first latency; Tread indicates a clock cycle in which the read pointer performs a read operation on the FIFO memory; and ┌•┐ indicates round-up.

### Claim 4 (depends on 1)

The method according to claim 1, wherein a clock frequency at which the write pointer performs a write operation on the FIFO memory and a clock frequency at which the read pointer performs a read operation on the FIFO memory are synchronous; and
wherein a clock phase at which the write pointer performs a write operation on the FIFO memory and a clock phase at which the read pointer performs a read operation on the FIFO memory are synchronous.

### Claim 5 (depends on 1)

The method according to claim 1, wherein receiving, by the first network device, the packet at the first time comprises:
receiving, by the first network device at the first time, the packet from a remote radio unit (RRU); or
receiving, by the first network device at the first time, the packet from a baseband unit (BBU).

### Claim 6

A method, comprising:
receiving, by a first network device, a packet that is from a second network device, wherein the packet carries a first time, and the first time is a time at which the second network device receives the packet;
processing, by the first network device, the packet to obtain a processed packet, and writing the processed packet into a buffer memory;
reading, by the first network device, the processed packet from the buffer memory at a second time;
determining, by the first network device at a time after the second time, a first latency of the processed packet in a first in first out (FIFO) memory, wherein the first latency is equal to a difference obtained by subtracting a second latency from a target latency, the target latency is equal to a period from the first time to a third time at which the processed packet is forwarded by the first network device through an egress port, the second latency is equal to a sum of a third latency and a fourth latency, the third latency is equal to a period from the first time to the second time, the fourth latency is a fixed latency, and the FIFO memory comprises multiple contiguous storage units;
setting, by the first network device, a read pointer and/or a write pointer according to the determined first latency;
writing, by the first network device according to the set write pointer, the processed packet into a storage unit in the FIFO memory, or reading, according to the set read pointer, the processed packet from a storage unit in the FIFO memory; and
forwarding, by the first network device at the third time through the egress port, the processed packet that is read from the FIFO memory.

### Claim 7 (depends on 6)

The method according to claim 6, wherein setting, by the first network device, the write pointer according to the first latency comprises:
determining, by the first network device according to the first latency, a location of the storage unit in the FIFO memory; and
setting, by the first network device according to the determined location of the storage unit, the write pointer to point to the storage unit.

### Claim 8 (depends on 7)

The method according to claim 7, wherein determining, by the first network device according to the first latency, the location of the storage unit in the FIFO memory comprises:
determining, by the first network device, the location of the storage unit in the FIFO memory according to the following formula:
P_add
=
⌈
T
1
T
read
⌉
-
1
,
wherein P_add indicates a quantity of storage units between a first storage unit and a second storage unit, wherein the first storage unit and the second storage unit are storage units in the multiple contiguous storage units, the first storage unit is configured to store the processed packet, the multiple contiguous storage units are configured to store a packet queue, each storage unit is configured to store only one packet or null data, and the second storage unit is configured to store a tail of the packet queue; T1 indicates the first latency; Tread indicates a clock cycle in which the read pointer performs a read operation on the FIFO memory; and ┌•┐ indicates round-up.

### Claim 9 (depends on 6)

The method according to claim 6, wherein Precision Time Protocol or Network Time Protocol is used to perform time synchronization between the first network device and the second network device.

### Claim 10 (depends on 6)

The method according to claim 6, wherein receiving, by the first network device, the packet comprises:
receiving, by the first network device, the packet from a remote radio unit (RRU); or
receiving, by the first network device, the packet from a baseband unit (BBU).

### Claim 11

An apparatus, comprising:
a receiver, configured to receive a packet at a first time;
a processor; and
a computer-readable storage medium storing a program to be executed by the processor, the program including instructions for:
processing the packet to obtain a processed packet, and write the processed packet into a buffer memory;
reading, from the buffer memory at a second time, the processed packet;
determining, at a time after the second time, a first latency of the processed packet in a first in first out (FIFO) memory, wherein the first latency is equal to a difference obtained by subtracting a second latency from a target latency, the target latency is equal to a period from the first time to a third time at which the processed packet is forwarded through an egress port, the second latency is equal to a sum of a third latency and a fourth latency, the third latency is equal to a period from the first time to the second time, the fourth latency is a fixed latency, and the FIFO memory comprises multiple contiguous storage units;
setting a read pointer and/or a write pointer according to the first latency;
writing, according to the set write pointer, the processed packet into a storage unit in the FIFO memory, or read, according to the set read pointer, the processed packet from a storage unit in the FIFO memory; and
forwarding, at the third time through the egress port, the processed packet that is read from the FIFO memory.

### Claim 12 (depends on 11)

The apparatus according to claim 11, wherein the program further includes instructions for:
determining, according to the first latency, a location of the storage unit in the FIFO memory; and
setting the write pointer according to the determined location of the storage unit, wherein the set write pointer points to the storage unit.

### Claim 13 (depends on 12)

The apparatus according to claim 12, wherein the program further includes instructions for:
determining the location of the storage unit in the FIFO memory according to the following formula:
P_add
=
⌈
T
1
T
read
⌉
-
1
,
wherein P_add indicates a quantity of storage units between a first storage unit and a second storage unit, wherein the first storage unit and the second storage unit are storage units in the multiple contiguous storage units, the first storage unit is configured to store the processed packet, the multiple contiguous storage units are configured to store a packet queue, each storage unit is configured to store only one packet or null data, and the second storage unit is configured to store a tail of the packet queue; T1 indicates the first latency; Tread indicates a clock cycle in which the read pointer performs a read operation on the FIFO memory; and ┌•┐ indicates round-up.

### Claim 14 (depends on 11)

The apparatus according to claim 11, wherein a clock frequency at which the write pointer performs a write operation on the FIFO memory and a clock frequency at which the read pointer performs a read operation on the FIFO memory are synchronous; and
wherein a clock phase at which the write pointer performs a write operation on the FIFO memory and a clock phase at which the read pointer performs a read operation on the FIFO memory are synchronous.

### Claim 15 (depends on 11)

The apparatus according to claim 11, wherein the receiver configured to:
receive, at the first time, the packet from a remote radio unit (RRU); or
receive, at the first time, the packet from a baseband unit (BBU).

### Claim 16

An apparatus, comprising:
a receiver, configured to receive a packet that is from a second network device, wherein the packet carries a first time, and the first time is a time at which the second network device receives the packet;
a processor; and
a computer-readable storage medium storing a program to be executed by the processor, the program including instructions for:
processing the packet to obtain a processed packet, and writing the processed packet into a buffer memory;
reading, from the buffer memory at a second time, the processed packet;
determining, at a time after the second time, a first latency of the processed packet in a first in first out (FIFO) memory, wherein the first latency is equal to a difference obtained by subtracting a second latency from a target latency, the target latency is equal to a period from the first time to a third time at which the processed packet is forwarded through an egress port, the second latency is equal to a sum of a third latency and a fourth latency, the third latency is equal to a period from the first time to the second time, the fourth latency is a fixed latency, and the FIFO memory comprises multiple contiguous storage units;
setting a read pointer and/or a write pointer according to the first latency;
writing, according to the set write pointer, the processed packet into a storage unit in the FIFO memory, or reading, according to the set read pointer, the processed packet from a storage unit in the FIFO memory; and
forwarding, at the third time through the egress port, the processed packet that is read from the FIFO memory.

### Claim 17 (depends on 16)

The apparatus according to claim 16, wherein the program further includes instructions for:
determining, according to the first latency, a location of the storage unit in the FIFO memory; and
setting, according to the determined location of the storage unit, the write pointer to point to the storage unit.

### Claim 18 (depends on 17)

The apparatus according to claim 17, wherein the program further includes instructions for:
determining the location of the storage unit in the FIFO memory according to the following formula:
P_add
=
⌈
T
1
T
read
⌉
-
1
wherein P_add indicates a quantity of storage units between a first storage unit and a second storage unit, wherein the first storage unit and the second storage unit are storage units in the multiple contiguous storage units, the first storage unit is configured to store the processed packet, the multiple contiguous storage units are configured to store a packet queue, each storage unit is configured to store only one packet or null data, and the second storage unit is configured to store a tail of the packet queue; T1 indicates the first latency; Tread indicates a clock cycle in which the read pointer performs a read operation on the FIFO memory; and ┌•┐ indicates round-up.

### Claim 19 (depends on 16)

The apparatus according to claim 16, wherein Precision Time Protocol or Network Time Protocol is used to perform time synchronization between the apparatus and the second network device.

### Claim 20 (depends on 16)

The apparatus according to claim 16, wherein the receiver is configured to:
receive the packet from a remote radio unit (RRU); or
receive the packet from a baseband unit (BBU).