Finite impulse response analog receive filter with amplifier-based delay chain

A channel interface module comprising:

• multiple amplifier-based delay circuits arranged in a sequential chain to convert an analog input signal into a set of increasingly-delayed analog signals that are weighted and combined together with the analog input signal to form an equalized signal, each amplifier-based delay circuit in the sequential chain including a sequence of multiple delay cells each employing a cascode transistor for a common source amplifier and a source follower stage including a transistor configured to provide a source follower output to introduce additional delay to the analog input signal;
• a symbol decision circuit operating on the equalized signal to obtain a sequence of symbol decisions:
• and
• an interface that extracts received data from the sequence of symbol decisions.

A channel interface module comprising:

• multiple amplifier-based delay circuits arranged in a sequential chain to convert an analog input signal into a set of increasingly-delayed analog signals that are weighted and combined together with the analog input signal to form an equalized signal, each amplifier-based delay circuit including one or more delay cells each employing a differential common source amplifier with adjustable source degeneration to introduce additional delay to the analog input signal;
• wherein the differential common source amplifier within each delay cell comprises:
• a pair of MOS transistors with gates that receive a differential input signal to the delay cell and drains that each are coupled to the respective gate by a gate-to-drain capacitance in excess of an intrinsic value for the MOS transistors;
• a symbol decision circuit operating on the equalized signal to obtain a sequence of symbol decisions;
• and
• an interface that extracts received data from the sequence of symbol decisions.

A method for providing high speed equalization, the method comprising:

• obtaining an analog receive signal from a communications channel;
• using a chain of amplifier-based delay circuits to convert the analog receive signal into a set of increasingly-delayed analog signals that are weighted and combined together with the analog received signal to form an equalized signal, each of said amplifier-based delay circuits having one or more delay cells, each of said one or more delay cells:
• receiving a delay cell input signal with a gate of a MOS transistor in a cascode amplifier configuration, said receiving including coupling the input signal from the gate to a drain of the MOS transistor with a gate-to-drain capacitance in excess of an intrinsic value for the MOS transistor, and
• buffering an output of that delay cell with a source follower output stage;
• sampling the equalized signal to obtain a sequence of symbol decisions;
• and
• extracting received data from the sequence of symbol decisions.

A method for providing high speed equalization, the method comprising:

• obtaining an analog receive signal from a communications channel, the analog receive signal being a differential signal;
• using a chain of amplifier-based delay circuits to convert the analog receive signal into a set of increasingly-delayed analog signals that are weighted and combined together with the analog received signal to form an equalized signal, each amplifier-based delay circuit accepting a differential input signal with a differential cascade amplifier stage including cascade transistors and providing a differential output signal by a source follower stage including transistors with an output buffer stage;
• sampling the equalized signal to obtain a sequence of symbol decisions;
• and
• extracting received data from the sequence of symbol decisions.