# US 10,313,157 B2 · Apparatus and method for multiplexing multi-lane multi-mode data transport > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,313,157 B2 - Document ID: US10313157B2 - Status: Granted - Kind: B2 - Application number: 15/646,147 - Filed: 2017-07-11 - Published: 2018-10-25 - Granted: 2019-06-04 - Earliest claimed: 2017-04-25 - Assignees: Realtek Semiconductor Corp. - Applicants: Realtek Semiconductor Corp. - Inventors: Chi-Kung Kuan; Chia-Liang (Leon) Lin - Web page: https://patentgrep.com/patent/US10313157B2 ## CPC - H04L 12/66: Arrangements for connecting between networks having differing types of switching systems, e.g. gateways - G06F 3/0635: {by changing the path, e.g. traffic rerouting, path reconfiguration} - G06F 13/4022: {using switching circuits, e.g. switching matrix, connection or expansion network (G06F13/4009 takes precedence)} - H10W 72/90: Bond pads, in general - H04J 99/00: Subject matter not provided for in other groups of this subclass - H10W 72/5445: {being orthogonal to a side surface of the chip, e.g. parallel arrangements} - H10W 72/932: {Plan-view shape, i.e. in top view} - H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M) - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - H04J: MULTIPLEX COMMUNICATION (transmission in general H04B; peculiar to transmission of digital information H04L5/00; systems for the simultaneous or sequential transmission of more than one television signal H04N7/08; in exchanges H04Q11/00; stereophonic systems H04S) ## Abstract An apparatus includes: a semiconductor die including a first I/O (input/output) pad, a second I/O pad, a switch, and an internal processor, wherein the switch is configured to short the first I/O pad to the second I/O pad when a logical signal is asserted; and a semiconductor package including a first bond pad configured to electrically connect to the first I/O pad, a second bond pad configured to electrically connect to the second I/O pad, a first port configured to electrically connect to a pin of a multi-lane, multi-mode connector, a second port configured to electrically connect to an external processor, a first routing path configured to electrically connect the first port to the first bond pad, and a second routing path configured to electrically connect the second port to the second bond pad, wherein the external processor is configured to process an electrical signal at the second port in accordance with a first protocol when the logical signal is asserted, and the internal processor is configured to process an electrical signal at the first I/O pad in accordance with a second protocol when the logical signal is de-asserted. ## Claims ### Claim 1 An apparatus comprising: a semiconductor die including: a first I/O (input/output) pad, a second I/O pad, and a third I/O pad; a first internal processor configured to process an electrical signal at the first I/O pad in accordance with a first protocol, when a first logical signal is de-asserted, a second internal processor configured to process an electrical signal at the second I/O pad in accordance with the first protocol, when a second logical signal is de-asserted, a first switch configured to electrically connect the first I/O pad to the third I/O pad, when the first logical signal is asserted, and a second switch configured to electrically connect the second I/O pad to the third I/O pad when the second logical signal is asserted; and a semiconductor package including: a first bond pad configured to electrically connect to the first I/O pad, a second bond pad configured to electrically connect to the second I/O pad, a third bond pad configured to electrically connect to the third I/O pad, a first port configured to electrically connect to a first pin of a multi-lane, multi-mode connector, a second port configured to electrically connect to a second pin of the multi-lane, multi-mode connector, and a third port configured to electrically connect to an external processor configured to process an electrical signal at the third port in accordance with a second protocol, wherein the first port is electrically connected to the first bond pad via a first routing path, the second port is electrically connected to the second bond pad via a second routing path, and the third port is electrically connected to the third bond pad via a third routing path. ### Claim 2 (depends on 1) The apparatus of claim 1, wherein the first bond pad electrically connects to the first I/O pad via a first bond wire, the second bond pad electrically connects to the second I/O pad via a second bond wire, and the third bond pad electrically connects to the third I/O pad via a first bond wire. ### Claim 3 (depends on 1) The apparatus of claim 1, wherein the semiconductor package is a BGA (ball grid array) package. ### Claim 4 (depends on 1) The apparatus of claim 1, wherein the first port electrically connects to the first pin of the multi-lane, multi-mode connector via a first metal trace laid out on a PCB (printed circuit board), while the third port electrically connects to the external processor via a second metal trace laid out on the PCB. ### Claim 5 (depends on 1) The apparatus of claim 1, wherein the second protocol is a USB (universal serial bus) protocol, while the first protocol is a DisplayPort protocol. ### Claim 6 (depends on 2) The apparatus of claim 2, wherein the first bond wire and the third bond wire are substantially parallel and adjacent to each other. ### Claim 7 (depends on 2) The apparatus of claim 2, wherein the second bond wire and the third bond wire are substantially parallel and adjacent to each other. ### Claim 8 (depends on 3) The apparatus of claim 3, wherein the first routing path includes a metal trace. ### Claim 9 (depends on 3) The apparatus of claim 3, wherein the third routing path includes a via. ### Claim 10 (depends on 4) The apparatus of claim 4, wherein the first metal trace and the second metal trace are laid out on different layers of the PCB. ### Claim 11 (depends on 8) The apparatus of claim 8, wherein the first routing path further includes a via. ### Claim 12 A method comprising: electrically connecting a first port, a second port, and a third port of a semiconductor package to a first pin of a multi-lane, multi-mode connector, a second pin of the multi-lane, multi-mode connector, and an external processor, respectively, wherein the external processor is configured to process an electrical signal associated with the third port in accordance with a first protocol; electrically connecting the first port, the second port, and the third port to a first bond pad, a second bond pad, and a third bond pad of the semiconductor package, respectively; electrically connecting the first bond pad, the second bond pad, and the third bond pad to a first I/O pad, a second I/O pad, and a third I/O pad of a semiconductor die, respectively; electrically connecting the first I/O pad with the third I/O pad using a first switch in response to a first logical signal being asserted, else processing an electrical signal at the first I/O pad using a first internal processor in accordance with a second protocol; and electrically connecting the second I/O pad with the third I/O pad using a second switch in response to a second logical signal being asserted, else processing an electrical signal at the second I/O pad using a second internal processor in accordance with the second protocol. ### Claim 13 (depends on 12) The method of claim 12, wherein the first bond pad electrically connects to the first I/O pad via a first bond wire, the second bond pad electrically connects to the second I/O pad via a second bond wire, and the third bond pad electrically connects to the third I/O pad via a third bond wire. ### Claim 14 (depends on 12) The method of claim 12, wherein the semiconductor package is a BGA (ball grid array) package. ### Claim 15 (depends on 12) The method of claim 12, wherein the first port electrically connects to the first pin of the multi-lane, multi-mode connector via a first metal trace laid out on a PCB (printed circuit board), while the third port electrically connects to the external processor via a second metal trace laid out on the PCB. ### Claim 16 (depends on 12) The method of claim 12, wherein the first protocol is a USB (universal serial bus) protocol, while the second protocol is a DisplayPort protocol. ### Claim 17 (depends on 13) The method of claim 13, wherein the first bond wire and third bond wire are substantially parallel and adjacent to each other. ### Claim 18 (depends on 13) The method of claim 13, wherein the second bond wire and third bond wire are substantially parallel and adjacent to each other. ### Claim 19 (depends on 14) The method of claim 14, wherein the first routing path includes a metal trace. ### Claim 20 (depends on 15) The method of claim 15, wherein the first metal trace and the second metal trace are laid out on different layers of the PCB.