# US 10,313,108 B2 · Energy-efficient bitcoin mining hardware accelerators > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,313,108 B2 - Document ID: US10313108B2 - Status: Granted - Kind: B2 - Application number: 15/196,686 - Filed: 2016-06-29 - Published: 2018-01-04 - Granted: 2019-06-04 - Earliest claimed: 2016-06-29 - Assignees: Intel Corporation - Applicants: Intel Corporation - Inventors: Vikram B. Suresh; Sudhir K. Satpathy; Sanu K. Mathew - Web page: https://patentgrep.com/patent/US10313108B2 ## CPC - H04L 9/0643: {Hash functions, e.g. MD5, SHA, HMAC or f9 MAC} - H04L 9/0618: {Block ciphers, i.e. encrypting groups of characters of a plain text message using fixed encryption transformation} - H04L 9/50: {using hash chains, e.g. blockchains or hash trees} - H04L 2209/20: Manipulating the length of blocks of bits, e.g. padding or block truncation - H04L 2209/30: Compression, e.g. Merkle-Damgard construction - H04L 2209/56: Financial cryptography, e.g. electronic payment or e-cash - H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M) ## Abstract A processing system includes a processor to construct an input message comprising a target value and a nonce and a hardware accelerator, communicatively coupled to the processor, implementing a plurality of circuits to perform stage-1 secure hash algorithm (SHA) hash and stage-2 SHA hash, wherein to perform the stage-2 SHA hash, the hardware accelerator is to perform a plurality of rounds of compression on state data stored in a plurality of registers associated with a stage-2 SHA hash circuit using an input value, calculate a plurality of speculative computation bits using a plurality of bits of the state data, and transmit the plurality of speculative computation bits to the processor. ## Claims ### Claim 1 A processing system comprising: a processor to construct an input message comprising a target value and a nonce; and a hardware accelerator, communicatively coupled to the processor, implementing a plurality of circuits to perform stage-1 secure hash algorithm (SHA) hash and stage-2 SHA hash based on the input message, wherein to perform the stage-2 SHA hash, the hardware accelerator is to: perform a plurality of rounds of compression on state data stored in a plurality of registers associated with a stage-2 SHA hash circuit using an input value, wherein the input value comprises a hash value generated by a stage-1 SHA hash circuit, and wherein each register of the plurality of registers is to store a state that is updated through the plurality of rounds of compression; calculate a plurality of speculative computation bits using a plurality of bits of the state data; and transmit the plurality of speculative computation bits to the processor. ### Claim 2 (depends on 1) The processing system of claim 1, wherein the processor is to: receive, from the hardware accelerator, the plurality of speculative computation bits; determine whether at least one bit of the plurality of speculative computation bits is non-zero; and responsive to determining that at least one bit of the plurality of speculative computation bits is non-zero, determine that the nonce is invalid. ### Claim 3 (depends on 2) The processing system of claim 2, wherein the processor is further to: prior to calculating the plurality of speculative computation bits, copy contents of the plurality of registers associated with the stage-2 SHA hash circuit to a second plurality of registers; responsive to determining that all of the plurality of speculative computation bits are zeros, copy contents of the second plurality of registers to the plurality of registers associated with the stage-2 SHA hash circuit; instruct the hardware accelerator to perform additional rounds of the compression using the stage-2 SHA hash circuit to generate a second hash value; receive, from the hardware accelerator, the second hash value; and compare the second hash value with the target value. ### Claim 4 (depends on 3) The processing system of claim 3, wherein the processor is further to: responsive to determining that the second hash value is one of greater than or same as the target value, determine that the nonce is invalid; and responsive to determining that the second hash value is smaller than the target value, determine that the nonce is a valid proof of identification of a Bitcoin coin. ### Claim 5 (depends on 4) The processing system of claim 4, wherein the processor is further to: responsive to determining validity of the nonce, increment a value of the nonce to generate an updated input message; and transmit the updated input message to the hardware accelerator to validate the incremented nonce. ### Claim 6 (depends on 1) The processing system of claim 1, wherein the input message comprises 1024 bits, the target value comprises 256 bit, and the nonce comprises 32 bits, wherein the plurality of rounds of compression comprise fewer than 64 rounds, the plurality of registers comprise eight 32-bit registers to store 256-bit state data, each 32-bit register storing a 32-bit state, and wherein the plurality of speculative computation bits comprises two bits, and wherein round 57 of the compression employs 221 bits of the 256-bit state data, round 58 of the compression employs 189 bits of the 256-bit state data, round 59 of the compression employs 142 bits of the 256-bit state data, and round 60 of the compression employs 16 bits of the 256-bit state data. ### Claim 7 (depends on 6) The processing system of claim 6, wherein the 1024-bit input message further comprises a 256-bit hash value recorded in a last block of a block chain recorded in a public ledger, a 256-bit Merkle root that is an initial hash value recorded in a first block of the block chain, a 32-bit time stamp, and a plurality of padding bits. ### Claim 8 (depends on 7) The processing system of claim 7, wherein the SHA hash is a SHA-256 hash, and wherein the hardware accelerator is further to perform stage-0 SHA hash on a first 512 bits of the 1024-bits input message to generate a hash value which is used to initiate eight registers associated with the stage-1 SHA hash. ### Claim 9 (depends on 8) The processing system of claim 8, wherein the stage-1 SHA hash is to receive a second 512 bits of the 1024-bit input message as an input value to the stage-1 SHA hash and to use the input value to the stage-1 SHA hash to perform 64 rounds of compression on 256-bit state data stored in the eight registers associated with stage-1 SHA hash. ### Claim 10 An application specific integrated circuit (ASIC) comprising: a plurality of registers; and a plurality of circuits to perform stage-1 secure hash algorithm (SHA) hash and stage-2 SHA hash, wherein to perform the stage-2 SHA hash based on an input message, the ASIC is to: perform a plurality of rounds of compression on state data stored in a plurality of registers associated with a stage-2 SHA hash circuit using an input value, wherein the input value comprises a hash value generated by a stage-1 SHA hash circuit, and wherein each register of the plurality of registers is to store a state that is updated through the plurality of rounds of compression; calculate a plurality of speculative computation bits using a plurality of bits of the state data; and transmit the plurality of speculative computation bits to a processor communicatively coupled to the ASIC. ### Claim 11 (depends on 10) The ASIC of claim 10, wherein the processor is to: receive, from the ASIC, the plurality of speculative computation bits; determine whether at least one bit of the plurality of speculative computation bits is non-zero; and responsive to determining that at least one bit of the plurality of speculative computation bits is non-zero, determine that a nonce is invalid. ### Claim 12 (depends on 11) The ASIC of claim 11, wherein the processor is further to: prior to calculating the plurality of speculative computation bits, copy contents of the plurality of registers associated with the stage-2 SHA hash circuit to a second plurality of registers; responsive to determining that all of the plurality of speculative computation bits are zeros, copy contents of the second plurality of registers to the plurality of registers associated with the stage-2 SHA hash circuit; instruct the ASIC to perform additional rounds of the compression using the stage-2 SHA hash circuit to generate a second hash value; receive, from the ASIC, the second hash value; and compare the second hash value with a target value. ### Claim 13 (depends on 12) The ASIC of claim 12, wherein the processor is further to: responsive to determining that the second hash value is one of greater than or same as the target value, determine that the nonce is invalid; and responsive to determining that the second hash value is smaller than the target value, determine that the nonce is a valid proof of identification of a Bitcoin coin. ### Claim 14 (depends on 13) The ASIC of claim 13, wherein the processor is further to: responsive to determining validity of the nonce, increment a value of the nonce to generate an updated input message; and transmit the updated input message to the ASIC to validate the incremented nonce. ### Claim 15 (depends on 10) The ASIC of claim 10, wherein the input message comprises 1024 bits comprising a 256-bit target value and a 32-bit nonce, wherein the plurality of rounds of compression comprise fewer than 64 rounds, the plurality of registers comprise eight 32-bit registers to store 256-bit state data, each 32-bit register storing a 32-bit state, and wherein the plurality of speculative computation bits comprises two bits, and wherein round 57 of the compression employs 221 bits of the 256-bit state data, round 58 of the compression employs 189 bits of the 256-bit state data, round 59 of the compression employs 142 bits of the 256-bit state data, and round 60 of the compression employs 16 bits of the 256-bit state data. ### Claim 16 (depends on 15) The ASIC of claim 15, wherein the ASIC is to receive, from the processor, the 1024-bit input message comprising the 256-bit target value, the 32-bit nonce, a 256-bit hash value recorded in a last block of a block chain recorded in a public ledger, a 256-bit Merkle root that is an initial hash value recorded in a first block of the block chain, a 32-bit time stamp, and a plurality of padding bits. ### Claim 17 (depends on 16) The ASIC of claim 16, wherein the SHA hash is a SHA-256 hash, and wherein the ASIC is further to perform stage-0 SHA hash on a first 51 bits of the 1024-bits input message to generate a hash value which is used to initiate eight registers associated with the stage-1 SHA hash, and the stage-1 SHA hash is to receive a second 512 bits of the 1024-bit input message as an input value to the stage-1 SHA hash and to use the input value to the stage-1 SHA hash to perform 64 rounds of compression on 256-bit state data stored in the eight registers associated with stage-1 SHA hash. ### Claim 18 A method comprising: transmitting, by a processor, an input message to a hardware accelerator, the input message comprising a target value and a nonce, wherein the hardware accelerator implements a plurality of circuits to perform stage-1 secure hash algorithm (SHA) hash and stage-2 SHA hash; instructing the hardware accelerator to perform a plurality of rounds of compression on state data stored in a plurality of registers associated with a stage-2 SHA hash circuit using an input value, wherein the input value comprises a hash value generated by a stage-1 SHA hash circuit, and wherein each register of the plurality of registers is to store a state that is updated through the plurality of rounds of compression; instructing the hardware accelerator to calculate a plurality of speculative computation bits using a plurality of bits of the state data; and receiving, from the hardware accelerator, the plurality of speculative computation bits. ### Claim 19 (depends on 18) The method of claim 18, further comprising: determining whether at least one bit of the plurality of speculative computation bits is non-zero; and responsive to determining that at least one bit of the plurality of speculative computation bits is non-zero, determining that the nonce is invalid. ### Claim 20 (depends on 19) The method of claim 19, further comprising: prior to calculating the plurality of speculative computation bits, copying contents of the plurality of registers associated with the stage-2 SHA hash circuit to a second plurality of registers; responsive to determining that all of the plurality of speculative computation bits are zeros, copying contents of the second plurality of registers to the plurality of registers associated with the stage-2 SHA hash circuit; instructing the hardware accelerator to perform additional rounds of the compression using the stage-2 SHA hash circuit to generate a second hash value; receiving, from the hardware accelerator, the second hash value; comparing the second hash value with the target value; responsive to determining that the second hash value is one of greater than or same as the target value, determining that the nonce is invalid; and responsive to determining that the second hash value is smaller than the target value, determining that the nonce is a valid proof of identification of a Bitcoin coin.