# US 10,313,104 B2 · System and method for controlling the impact of periodic jitter caused by non-ideal phase interpolators > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,313,104 B2 - Document ID: US10313104B2 - Status: Granted - Kind: B2 - Application number: 15/707,665 - Filed: 2017-09-18 - Published: 2019-03-21 - Granted: 2019-06-04 - Earliest claimed: 2017-09-18 - Assignees: Avago Technologies International Sales Pte. Limited - Applicants: Avago Technologies International Sales Pte. Limited - Inventors: Amiad Dvir; Mike Rolfe Ferrara; Vitaly Zborovski; Mario Caresosa; Ryan Hirth; Assaf Naor - Web page: https://patentgrep.com/patent/US10313104B2 ## CPC - H04L 7/033: using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop - H03L 7/00: Automatic control of frequency or phase; Synchronisation - H04B 1/00: Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission - H04L 7/0079: {Receiver details} - H04L 7/0087: {Preprocessing of received signal for synchronisation, e.g. by code conversion, pulse generation or edge detection} - H04L 43/087: Jitter - H04J 3/0685: {Clock or time synchronisation in a node; Intranode synchronisation} - H04L 7/0337: {Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals} - H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M) - H03L: AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES (generation of oscillations H03B) - H04B: TRANSMISSION - H04J: MULTIPLEX COMMUNICATION (transmission in general H04B; peculiar to transmission of digital information H04L5/00; systems for the simultaneous or sequential transmission of more than one television signal H04N7/08; in exchanges H04Q11/00; stereophonic systems H04S) ## Abstract In some aspects, the disclosure is directed to methods and systems for controlling periodic jitter arising from a phase interpolator (PI). A receiver can receive incoming data. A fractional-N phase-locked loop (PLL) can receive a reference clock. Measurement circuitry can measure a parts per million (PPM) offset between the incoming data and the reference clock, of a PI. The fractional-N PLL can restrict jitter arising from the PI, to frequencies within a predefined bandwidth, by tuning a center frequency of the fractional-N PLL to reduce the PPM offset of the PI. ## Claims ### Claim 1 A method for controlling periodic jitter arising from a phase interpolator (PI), comprising: receiving incoming data; receiving a reference clock of a fractional-N phase-locked loop (PLL), wherein N is an integer; measuring a parts per million (PPM) offset between the incoming data and the reference clock, of a first PI; and restricting jitter arising from the first PI, to frequencies within a predefined bandwidth, by tuning a center frequency of the fractional-N PLL to reduce the PPM offset of the first PI, wherein the jitter arising from the first PI comprises jitter arising from non-linear phases of the first PI. ### Claim 2 (depends on 1) The method of claim 1, further comprising reducing the PPM offset of the first PI to a target value or to be within a target value range. ### Claim 3 (depends on 1) The method of claim 1, further comprising reducing the jitter arising from the first PI by reducing a frequency shift of the first PI or a frequency shift required by the first PI. ### Claim 4 (depends on 1) The method of claim 1, further comprising reducing the jitter arising from the first PI by shifting a component of the jitter to reside outside of a predefined frequency range. ### Claim 5 (depends on 1) The method of claim 1, further comprising performing clock and data recovery (CDR) using the incoming data and the reference clock. ### Claim 6 (depends on 1) The method of claim 1, wherein receiving the incoming data comprises receiving the incoming data from a high speed serial communications link. ### Claim 7 (depends on 1) The method of claim 1, wherein tuning a center frequency of the fractional-N PLL comprises adjusting the center frequency to or towards a desired frequency for transmitting outgoing data. ### Claim 8 A method for controlling periodic jitter arising from a phase interpolator (PI), comprising: receiving incoming data; receiving a reference clock of a phase-locked loop (PLL); measuring a parts per million (PPM) offset between the incoming data and the reference clock, of a first PI; and restricting jitter arising from the first PI, to frequencies within a predefined bandwidth, by tuning a center frequency of the PLL using a digital-analog converter (DAC) to reduce the PPM offset of the first PI, wherein the jitter arising from the first PI comprises jitter arising from non-linear phases of the first PI. ### Claim 9 (depends on 8) The method of claim 8, further comprising reducing the PPM offset of the first PI to a target value or to be within a target value range. ### Claim 10 (depends on 8) The method of claim 8, further comprising reducing the jitter arising from the first PI by reducing a frequency shift of the first PI or a frequency shift required by the first PI. ### Claim 11 (depends on 8) The method of claim 8, further comprising reducing the jitter arising from the first PI by shifting a component of the jitter to reside outside of a predetermined frequency range. ### Claim 12 (depends on 8) The method of claim 8, further comprising performing clock and data recovery (CDR) using the incoming data and the reference clock. ### Claim 13 (depends on 8) The method of claim 8, wherein receiving the incoming data comprises receiving the incoming data from a high speed serial communications link. ### Claim 14 (depends on 8) The method of claim 8, wherein restricting jitter arising from the first PI, to frequencies within a predefined bandwidth comprises setting a configuration of the DAC in a continuous mode. ### Claim 15 A system for controlling periodic jitter arising from a phase interpolator (PI), comprising: a receiver configured to receive incoming data; a fractional-N phase-locked loop (PLL) configured to receive a reference clock, wherein N is an integer; and measurement circuitry configured to measure a parts per million (PPM) offset between the incoming data and the reference clock, of a first PI, wherein the fractional-N PLL is further configured to restrict jitter arising from the first PI, to frequencies within a predefined bandwidth, by tuning a center frequency of the fractional-N PLL to reduce the PPM offset of the first PI, wherein the jitter arising from the first PI comprises jitter arising from non-linear phases of the first PI. ### Claim 16 (depends on 15) The system of claim 15, wherein the fractional-N PLL is further configured to reduce the PPM offset of the first PI to a target value or to be within a target value range. ### Claim 17 (depends on 15) The system of claim 15, wherein the fractional-N PLL is further configured to reduce the jitter arising from the first PI by reducing a frequency shift of the first PI or a frequency shift required by the first PI. ### Claim 18 (depends on 15) The system of claim 15, wherein the fractional-N PLL is further configured to reduce the jitter arising from the first PI by shifting a component of the jitter to reside outside of a predetermined frequency range. ### Claim 19 (depends on 15) The system of claim 15, wherein the receiver is further configured to receive the incoming data from a high speed serial communications link. ### Claim 20 (depends on 15) The system of claim 15, wherein the fractional-N PLL is further configured to tune a center frequency of the fractional-N PLL by adjusting the center frequency to or towards a desired frequency for transmitting outgoing data.