# US 10,313,101 B2 · High-speed interface apparatus and deskew method thereof > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,313,101 B2 - Document ID: US10313101B2 - Status: Granted - Kind: B2 - Application number: 16/113,857 - Filed: 2018-08-27 - Published: 2019-02-21 - Granted: 2019-06-04 - Earliest claimed: 2014-02-13 - Assignees: Samsung Electronics Co., Ltd. - Applicants: Samsung Electronics Co., Ltd. - Inventors: Han Soo Lee; Sung Jun Kim; Chae Ryung Kim; Dong Uk Park; Youn Woong Chung; Jung Myung Choi; Han Kyul Lim; Gyeong Han Cha - Web page: https://patentgrep.com/patent/US10313101B2 ## CPC - H04L 7/0041: {Delay of data signal} - G01R 31/31725: {Timing aspects, e.g. clock distribution, skew, propagation delay (for tester hardware G01R31/31937)} - H03K 5/131: Digitally controlled - H04L 7/0016: {correction of synchronization errors} - H04L 25/14: Channel dividing arrangements {, i.e. in which a single bit stream is divided between several baseband channels and reassembled at the receiver} - H03K 2005/00058: {controlled by a digital setting} - H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M) - G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12) - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) ## Abstract A high-speed interface apparatus and method of correcting skew in the apparatus are provided. A high-speed transmitter includes a transmission D-PHY module that generates and transmits a clock signal through a clock channel, generates a deskew synchronous code and test data in response to a deskew request signal, transmits the deskew synchronous code followed by the test data through a data channel, and transmits a normal synchronous code followed by normal data through the data channel in normal mode. ## Claims ### Claim 1 A device comprising: a transmitter configured to sequentially transmit a deskew synchronous code and test data, and configured to sequentially transmit a normal synchronous code and normal data, wherein a pattern of the deskew synchronous code is different from a pattern of the normal synchronous code, and the deskew synchronous code includes 8-bit serial data “11111111”. ### Claim 2 (depends on 1) The device of claim 1, wherein the normal synchronous code includes 8-bit serial data “00011101”. ### Claim 3 (depends on 1) The device of claim 1, wherein the test data includes 8-bit serial data “01010101”. ### Claim 4 (depends on 1) The device of claim 1, wherein the transmitter is an application processor. ### Claim 5 (depends on 1) The device of claim 1, wherein the transmitter is an image sensor. ### Claim 6 (depends on 1) The device of claim 1, wherein the transmitter is configured to transmit differential signals as the normal data. ### Claim 7 (depends on 1) The device of claim 1, wherein the normal data is image data. ### Claim 8 (depends on 1) The device of claim 1, wherein the transmitter includes: a first transmission channel unit configured to transmit the deskew synchronous code and the test data through a first channel; and a second transmission channel unit configured to transmit the deskew synchronous code and the test data through a second channel. ### Claim 9 (depends on 8) The device of claim 8, wherein the transmitter includes a clock generator configured to transmit a clock signal through a clock channel. ### Claim 10 (depends on 9) The device of claim 9, wherein each of the first channel, the second channel, and the clock channel includes two lines. ### Claim 11 A device comprising: a receiver configured to sequentially receive a deskew synchronous code and test data, and configured to sequentially receive a normal synchronous code and normal data, wherein a pattern of the deskew synchronous code is different from a pattern of the normal synchronous code, and the deskew synchronous code includes 8-bit serial data “11111111”. ### Claim 12 (depends on 11) The device of claim 11, wherein the normal synchronous code includes 8-bit serial data “00011101”. ### Claim 13 (depends on 11) The device of claim 11, wherein the test data includes 8-bit serial data “01010101”. ### Claim 14 (depends on 11) The device of claim 11, wherein the receiver is an application processor. ### Claim 15 (depends on 11) The device of claim 11, wherein the receiver is a display serial interface device. ### Claim 16 (depends on 11) The device of claim 11, wherein the receiver s configured to receive differential signals as the normal data. ### Claim 17 (depends on 11) The device of claim 11, wherein the receiver includes: a first reception channel unit configured to receive the deskew synchronous code and the test data through a first channel; and a second reception channel unit configured to receive the deskew synchronous code and the test data through a second channel. ### Claim 18 (depends on 17) The device of claim 17, wherein the receiver includes a clock receiving unit configured to receive a clock signal through a clock channel. ### Claim 19 (depends on 18) The device of claim 18, wherein each of the first channel, the second channel, and the clock channel includes two lines. ### Claim 20 An application processor comprising: a transmitter D-PHY module configured to transmit a first normal synchronous code through a first channel and to transmit a first clock signal through a first clock channel; and a receiver D-PHY module configured to receive a second normal synchronous code through a second channel and to receive a second clock signal through a second clock channel, wherein the first normal synchronous code includes 8-bit serial data “00011101”.