# US 10,313,068 B1 · Signal monitoring and measurement for a multi-wire, multi-phase interface > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,313,068 B1 - Document ID: US10313068B1 - Status: Granted - Kind: B1 - Application number: 15/961,687 - Filed: 2018-04-24 - Granted: 2019-06-04 - Earliest claimed: 2018-04-24 - Assignees: QUALCOMM Incorporated - Applicants: QUALCOMM Incorporated - Inventors: Yasser Ahmed; Ying Duan - Web page: https://patentgrep.com/patent/US10313068B1 ## CPC - H04L 1/203: {Details of error rate determination, e.g. BER, FER or WER} - G06F 13/4278: {using an embedded synchronisation} - H04B 3/46: Monitoring; Testing - H04L 7/0087: {Preprocessing of received signal for synchronisation, e.g. by code conversion, pulse generation or edge detection} - H04L 25/0272: {Arrangements for coupling to multiple lines, e.g. for differential transmission} - H04L 1/205: {jitter monitoring} - H04L 7/0037: {Delay of clock signal} - H04L 7/033: using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop - H04L 25/0292: {Arrangements specific to the receiver end} - H04L 25/085: {Arrangements for reducing interference in line transmission systems, e.g. by differential transmission} - H04L 25/4925: {using balanced bipolar ternary codes} - H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M) - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - H04B: TRANSMISSION ## Abstract Methods, apparatus, and systems for monitoring and measuring signal characteristics for signals received over a multi-wire, multi-phase interface are disclosed. Signals present on each line of a 3-line communication interface are sampled using auxiliary samplers having a programmable time delay to delay the sampled signal by a set time, as well as a programmable voltage offset. The auxiliary sampler outputs are compared with direct line samples of signals on each of the three lines to generate error signals. From this comparison, an array of error signal data occurring over a particular sampling period may be generated. In turn, waveform characteristics can be determined from the error signal data, such as an eye-pattern. Furthermore, skew measurement may further be effectuated using the auxiliary samplers but determining the time difference of when the error signals of the different wires cross a predetermined threshold. ## Claims ### Claim 1 A method for characterizing a waveform received in a data communication device coupled to a 3-line communication interface, the method comprising: sampling signals present on each line of the 3-line communication interface using a plurality of first samplers, where a respective first sampler of the plurality of first samplers samples each line, wherein each sampler includes at least one of a programmable time delay and a programmable voltage offset configured to respectively delay the sampled signal by a time amount or determine a voltage offset; comparing the outputs of each first sampler with respective direct line samples of signals on each of the three lines of the 3-line communication interface to generate error signals, where the direct line samples are sampled using a plurality of second samplers, each of which is coupled to a respective line of the 3-line communication interface; generating an array of error signal data over time using the comparison of the sample outputs and the line samples; and determining waveform characteristics based on the array of error signal data. ### Claim 2 (depends on 1) The method of claim 1, wherein the determined waveform characteristics include a determined eye pattern. ### Claim 3 (depends on 1) The method of claim 1, wherein the error signals are generated using one or more XOR logic circuitry configured to compare the outputs of each first and second sampler with respective direct line samples of signals on each of the three lines of the 3-line communication interface to generate the error signals. ### Claim 4 (depends on 1) The method of claim 1, wherein the programmable time delay is based on a recovered clock signal determined in a clock and data recovery circuit within a receiver receiving the signals on the 3-line communication interface, such that the time delay is at least one delay step of a predetermined number of delay time steps of the recovered clock signal. ### Claim 5 (depends on 4) The method of claim 4, wherein each delay time step of the predetermined number of time steps is a prescribed delay time behind the recovered clock signal. ### Claim 6 (depends on 1) The method of claim 1, wherein the programmable voltage offset includes a plurality of predetermined voltage steps of voltages at which a first sampler will sample a respective line of the 3-line communication interface. ### Claim 7 (depends on 1) The method of claim 1, further comprising: determining skew between at least two lines of the three lines of the 3-line interface, comprising: setting an error signal threshold; determining at which time steps of a plurality of time delay steps the error signal from each of the at least two lines respectively falls below the error signal threshold; and determining the skew between the at least two lines based on the difference of the determined time steps of the respective lines. ### Claim 8 (depends on 1) The method of claim 1, wherein the 3-line interface is a C-PHY interface. ### Claim 9 An apparatus for characterizing a waveform received in a data communication device coupled to a 3-line communication interface, comprising: means for sampling signals present on each line of the 3-line communication interface using a plurality of first samplers, where a respective first sampler of the plurality of first samplers samples each line, wherein each sampler includes at least one of a programmable time delay and a programmable voltage offset configured to respectively delay the sampled signal by a time amount or determine a voltage offset; means for sampling direct line signals using a plurality of second samplers, means for comparing the outputs of each first sampler with respective direct line samples from each of the second samplers for each of the three lines of the 3-line communication interface to generate error signals; means for generating an array of error signal data over time using the comparison of the sample outputs and the line samples from the means for comparing; and means for determining waveform characteristics based on the array of error signal data. ### Claim 10 (depends on 9) The apparatus of claim 9, wherein the determined waveform characteristics include a determined eye pattern. ### Claim 11 (depends on 9) The apparatus of claim 9, wherein the means for comparing includes one or more XOR logic circuitry configured to compare the outputs of each first and second sampler with respective direct line samples of signals on each of the three lines of the 3-line communication interface to generate the error signals. ### Claim 12 (depends on 9) The apparatus of claim 9, wherein the programmable time delay is based on a recovered clock signal determined in a clock and data recovery circuit within a receiver receiving the signals on the 3-line communication interface, such that the time delay is at least one delay step of a predetermined number of delay time steps of the recovered clock signal. ### Claim 13 (depends on 12) The apparatus of claim 12, wherein each delay time step of the predetermined number of time steps is a prescribed delay time behind the recovered clock signal. ### Claim 14 (depends on 9) The apparatus of claim 9, wherein the programmable voltage offset includes a plurality of predetermined voltage steps of voltages at which a first sampler will sample a respective line of the 3-line communication interface. ### Claim 15 (depends on 9) The apparatus of claim 9, further comprising: means for determining skew between at least two lines of the three lines of the 3-line interface, comprising: means for setting an error signal threshold; means for determining at which time steps of a plurality of time delay steps the error signal from each of the at least two lines respectively falls below the error signal threshold; and means for determining the skew between the at least two lines based on the difference of the determined time steps of the respective lines. ### Claim 16 (depends on 9) The apparatus of claim 9, wherein the 3-line interface is a C-PHY interface. ### Claim 17 A non-transitory processor readable storage medium comprising code for: sampling signals present on each line of a 3-line communication interface using a plurality of first samplers, where a respective first sampler of the plurality of first samplers samples each line, wherein each sampler includes at least one of a programmable time delay and a programmable voltage offset configured to respectively delay the sampled signal by a time amount or determine a voltage offset; comparing the outputs of each first sampler with respective direct line samples of signals on each of the three lines of the 3-line communication interface to generate error signals, where the direct line samples are sampled using a plurality of second samplers, each of which is coupled to a respective line of the 3-line communication interface; generating an array of error signal data over time using the comparison of the sample outputs and the line samples; and determining waveform characteristics based on the array of error signal data. ### Claim 18 (depends on 17) The processor readable storage medium of claim 17, wherein the determined waveform characteristics include a determined eye pattern. ### Claim 19 (depends on 17) The processor readable storage medium of claim 17, wherein the error signals are generated using one or more XOR logic circuitry configured to compare the outputs of each first and second sampler with respective direct line samples of signals on each of the three lines of the 3-line communication interface to generate the error signals. ### Claim 20 (depends on 17) The processor readable storage medium of claim 17, wherein the programmable time delay is based on a recovered clock signal determined in a clock and data recovery circuit within a receiver receiving the signals on the 3-line communication interface, such that the time delay is at least one delay step of a predetermined number of delay time steps of the recovered clock signal. ### Claim 21 (depends on 20) The processor readable storage medium of claim 20, wherein each delay time step of the predetermined number of time steps is a prescribed delay time behind the recovered clock signal. ### Claim 22 (depends on 17) The processor readable storage medium of claim 17, wherein the programmable voltage offset includes a plurality of predetermined voltage steps of voltages at which a first sampler will sample a respective line of the 3-line communication interface. ### Claim 23 (depends on 17) The processor readable storage medium of claim 17, further comprising code for: determining skew between at least two lines of the three lines of the 3-line interface, comprising: setting an error signal threshold; determining at which time steps of a plurality of time delay steps the error signal from each of the at least two lines respectively falls below the error signal threshold; and determining the skew between the at least two lines based on the difference of the determined time steps of the respective lines. ### Claim 24 (depends on 17) The processor readable storage medium of claim 17, wherein the 3-line interface is a C-PHY interface. ### Claim 25 A system for characterizing a waveform received in a data communication device coupled to a 3-line communication interface, the system comprising: a first sampling circuitry in a receiver that is configured to sample signals present on each line of the 3-line communication interface, wherein the first sampling circuity includes at least one of a programmable time delay and a programmable voltage offset configured to respectively delay the sampled signal by a time delay amount or determine a voltage offset; a second sampling circuitry in the receiver that is configured to directly sample the signal on each line of the 3-line communication interface; a comparison circuitry configured to compare the outputs of the first sampling circuitry and the second sampling circuitry over a plurality of time delay amounts and a plurality of voltage offsets to generate a plurality of error signals; an error signal array generator configured to generate an array of error signal data over time using the plurality of error signals; and a waveform characteristic determination circuitry configured to determine waveform characteristics of the signals received on the 3-line communication interface based on the array of error signal data. ### Claim 26 (depends on 25) The system of claim 25, wherein the determined waveform characteristics include a determined eye pattern. ### Claim 27 (depends on 25) The system of claim 25, wherein the programmable time delay is based on a recovered clock signal determined in a clock and data recovery circuit within a receiver receiving the signals on the 3-line communication interface, such that the time delay is at least one delay step of a predetermined number of delay time steps of the recovered clock signal. ### Claim 28 (depends on 25) The system of claim 25, wherein the programmable voltage offset includes a plurality of predetermined voltage steps of voltages at which a first sampler will sample a respective line of the 3-line communication interface. ### Claim 29 (depends on 25) The system of claim 25, further comprising: skew determination circuitry configured for determining skew between at least two lines of the three lines of the 3-line interface, the circuitry comprising: circuitry for setting an error signal threshold; circuitry for determining at which time steps of a plurality of time delay steps the error signal from each of the at least two lines respectively falls below the error signal threshold; and circuitry for determining the skew between the at least two lines based on the difference of the determined time steps of the respective lines. ### Claim 30 (depends on 25) The system of claim 25, wherein the 3-line interface is a C-PHY interface.