# US 10,312,967 B2 · System and method for cross-talk cancellation in single-ended signaling

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- Number: US 10,312,967 B2
- Document ID: US10312967B2
- Status: Granted
- Kind: B2
- Application number: 14/970,415
- Filed: 2015-12-15
- Published: 2017-06-15
- Granted: 2019-06-04
- Earliest claimed: 2015-12-15
- Assignees: NVIDIA Corporation
- Applicants: NVIDIA Corporation
- Inventors: Xi Chen
- Web page: https://patentgrep.com/patent/US10312967B2

## CPC

- H04B 3/32: Reducing cross-talk, e.g. by compensating
- G11C 5/063: {Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay}
- G11C 7/18: Bit line organisation; Bit line lay-out
- H04L 25/0272: {Arrangements for coupling to multiple lines, e.g. for differential transmission}
- H04L 25/085: {Arrangements for reducing interference in line transmission systems, e.g. by differential transmission}
- H05K 3/222: {Completing of printed circuits by adding non-printed jumper connections (printed jumper connections H05K3/4685)}
- H04B: TRANSMISSION
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M)
- H05K: PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS

## Abstract

A method for transmitting data advantageously reduces cross-talk in high-speed data transmission. The method comprises receiving an input data word, encoding the input data word into a code word, and driving the code word on to an interconnect for transmission. The code word is generating using a balanced coding scheme, and the interconnect is a single-ended, twisted-wire on-chip fly-over interconnect. A receiver circuit decodes the code word to generate an output data word.

## Claims

### Claim 1

A method, comprising:
receiving an input data word for transmission, wherein the input data word includes two or more independent bits of digital data;
encoding the input data word into a code word; and
driving the code word, by a data transmitter circuit within a first region of a single integrated circuit die, on to an interconnect for transmission to a data receiver circuit within a second region of the single integrated circuit die, wherein the interconnect is a single-ended, twisted-wire on-chip fly-over interconnect between the first and second regions within the single integrated circuit die and comprises a double-twist structure at each boundary, and
the interconnect includes signal wires corresponding to bits comprising the code word, wherein the double-twist structure twists a first signal wire up at least one lane and twists a second signal wire down two lanes.

### Claim 2 (depends on 1)

The method of claim 1, wherein the interconnect is physically structured to include a set of segments, each segment comprising at least three lanes of the signal wires routed in parallel and the first signal wire of the signal wires is placed in a different one of the lanes as the first signal wire traverses each boundary between adjacent segments.

### Claim 3 (depends on 2)

The method of claim 2, wherein a number of the segments in the set of segments is an integer multiple of half a number of the signal wires.

### Claim 4

A system, comprising:
a single integrated circuit die fabricated to include:
an interconnect, wherein the interconnect is a single-ended, twisted-wire on-chip fly-over interconnect between a first region and a second region within the single integrated circuit die and comprises a double-twist structure at each boundary; and
a data transmitter circuit within the first region of the single integrated circuit die, configured to:
receive an input data word for transmission, wherein the input data word includes two or more independent bits of digital data;
encode the input data word into a code word; and
drive the code word on to the interconnect for transmission, wherein the interconnect includes signal wires corresponding to bits comprising the code word and the double-twist structure twists a first signal wire up at least one lane and twists a second signal wire down two lanes; and
a data receiver circuit fabricated within the second region of the single integrated circuit die and coupled to the interconnect to receive the code word.

### Claim 5 (depends on 4)

The system of claim 4, wherein the data receiver circuit is configured to decode the code word to generate an output data word, and the output data word is equivalent to the input data word.

### Claim 6 (depends on 4)

The system of claim 4, wherein the code word exhibits an equal number of low-going and high-going transitions for an arbitrary code word transition.

### Claim 7 (depends on 4)

The system of claim 4, wherein the interconnect is physically structured to include a set of segments, each segment comprising at least three lanes of the signal wires routed in parallel and the first signal wire of the signal wires is placed in a different one of the lanes as the first signal wire traverses each boundary between adjacent segments.

### Claim 8 (depends on 7)

The system of claim 7, wherein a number of the segments in the set of segments is an integer multiple of half a number of the signal wires.

### Claim 9 (depends on 7)

The system of claim 7, wherein the interconnect is structured to include a number of segments equal in number to a number of signal wires associated with the code word.

### Claim 10 (depends on 4)

The system of claim 4, wherein the single integrated circuit die further comprises a processing unit.

### Claim 11

An apparatus, comprising:
a single integrated circuit die fabricated to include:
an interconnect, wherein the interconnect is a single-ended, twisted-wire on-chip fly-over interconnect between a first region and a second region within the single integrated circuit die and comprises a double-twist structure at each boundary; and
a data transmitter circuit within a first region of the single integrated circuit die, configured to:
receive an input data word for transmission, wherein the input data word includes two or more independent bits of digital data;
encode the input data word into a code word; and
drive the code word on to the interconnect for transmission, wherein the interconnect includes signal wires corresponding to bits comprising the code word and the double-twist structure twists a first signal wire up at least one lane and twists a second signal wire down two lanes; and
a data receiver circuit that is configured to receive the code word that is transmitted through the interconnect.

### Claim 12 (depends on 11)

The apparatus of claim 11, wherein the data word comprises four independent bits of digital data and the code word includes six bits of digital data.

### Claim 13 (depends on 11)

The apparatus of claim 11, wherein the code word is generated to be a balanced code word.

### Claim 14 (depends on 13)

The apparatus of claim 13, wherein the balanced code word exhibits an equal number of low-going and high-going transitions for an arbitrary code word transition.

### Claim 15 (depends on 11)

The apparatus of claim 11, wherein each bit of the code word is phase-aligned during transmission.

### Claim 16 (depends on 11)

The apparatus of claim 11, wherein the data receiver circuit is further configured to decode the code word to generate an output data word, wherein the output data word is equivalent to the input data word.

### Claim 17 (depends on 11)

The apparatus of claim 11, wherein the interconnect is physically structured to include a set of segments, each segment comprising at least three lanes of the signal wires routed in parallel and the first signal wire of the signal wires is placed in a different one of the lanes as the first signal wire traverses each boundary between adjacent segments.

### Claim 18 (depends on 17)

The apparatus of claim 17, wherein a number of the segments in the set of segments is an integer multiple of half a number of the signal wires.

### Claim 19 (depends on 17)

The apparatus of claim 17, wherein the interconnect is structured to include a number of segments equal in number to a number of signal wires associated with the code word.