# US 10,312,944 B2 · Error correction code (ECC) operations in memory for providing redundant error correction

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- Number: US 10,312,944 B2
- Document ID: US10312944B2
- Status: Granted
- Kind: B2
- Application number: 15/461,623
- Filed: 2017-03-17
- Published: 2018-09-20
- Granted: 2019-06-04
- Earliest claimed: 2017-03-17
- Assignees: Micron Technology, Inc.
- Applicants: Micron Technology, Inc.
- Inventors: Patrick R. Khayat; Sivagnanam Parthasarathy; Mustafa N. Kaynak
- Web page: https://patentgrep.com/patent/US10312944B2

## CPC

- H03M 13/2948: {Iterative decoding (H03M13/2957 takes precedence)}
- H03M 13/2906: {using block codes (H03M13/2957 takes precedence)}
- H03M 13/2918: {with error correction codes in three or more dimensions, e.g. 3-dimensional product code where the bits are arranged in a cube}
- H03M 13/2927: {Decoding strategies}
- H03M 13/2945: {using at least three error correction codes (H03M13/2957 takes precedence)}
- H03M 13/152: {Bose-Chaudhuri-Hocquenghem [BCH] codes}
- H03M 13/2909: {Product codes}
- H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C)

## Abstract

Apparatuses and methods for performing an error correction code (ECC) operation are provided. One example method can include encoding data by including parity data for a number of cross-over bits, wherein the number of cross-over bits are bits located at intersections of column codewords and row codewords.

## Claims

### Claim 1

A method for performing an error correction code (ECC) operation, comprising:
writing data to a memory device, wherein writing the data includes encoding the data by including parity data for a number of cross-over bits, wherein the number of cross-over bits are bits located at intersections of column codewords and row codewords, wherein the parity data for the number of cross-over bits is a result of an XOR operation on the bits located at the intersections of intersections of column codewords and row codewords, and wherein the column codewords and row codewords are encoded with block-wise concatenated product codes;
reading the data from the memory device, wherein reading the data includes correcting errors in the data by performing a decoding operation on the data using the parity data for the number of cross-over bits and computing a cross-over bits parity syndrome; and
performing an XOR operation on the cross-over bits parity syndrome and the number of cross-over bits in response to a syndrome of the decoding operation being non-zero and errors associated with an 11 stall pattern.

### Claim 2 (depends on 1)

The method of claim 1, further including performing an XOR operation on each of the number of cross-over bits located at the intersections of column codewords and row codewords to create the parity data for the number of cross-over bits.

### Claim 3 (depends on 1)

The method of claim 1, further including storing the parity data for the number of cross over bits in an array of memory cells.

### Claim 4 (depends on 1)

The method of claim 1, further including encoding data by creating block-wise concatenated codewords.

### Claim 5 (depends on 1)

The method of claim 1, further including encoding the data with a first encoder, creating the parity data for the number of cross-over bits that were created while encoding data with the first encoder, and encoding the data with a second encoder.

### Claim 6

A method performing an error correction code (ECC) operation, comprising:
writing data to a memory device, wherein writing the data includes:
encoding the data with a first encoder;
creating parity data for cross-over bits created by the first encoder, wherein the cross-over bits are bits located at intersections of block-wise concatenated column codewords and row codewords;
encoding the data with a second encoder; and
reading the data from the memory device, wherein reading the data includes correcting errors in the data by performing a decoding operation on the data using the parity data for cross-over bits and computing a cross-over bits parity syndrome; and
performing an XOR operation on the cross-over bits parity syndrome and the cross-over bits in response to the cross-over bits parity syndrome being non-zero and errors associated with an 11 stall pattern.

### Claim 7 (depends on 6)

The method of claim 6, further including correcting an error in the data using the parity data for the cross-over bits, wherein the error in the data is located at a particular intersection of column codewords and row codewords.

### Claim 8 (depends on 6)

The method of claim 6, wherein the first encoder and the second encoder are BCH encoders.

### Claim 9 (depends on 6)

The method of claim 6, wherein the method includes storing the encoded data in an array of memory cells.

### Claim 10 (depends on 9)

The method of claim 9, wherein storing the encoded data includes storing codewords that include user data, column codeword parity data, row codeword parity data, and first encoder parity data.

### Claim 11 (depends on 6)

The method of claim 6, wherein the method includes storing the parity data for cross-over bits in a portion of the codewords stored in the array.

### Claim 12 (depends on 6)

The method of claim 6, wherein the method includes storing the parity data for cross-over bits in the portion of codewords that have less first encoder parity data than other portions of codewords.

### Claim 13

A method performing an error correction code (ECC) operation, comprising:
reading data from a memory device, wherein reading the data includes correcting an error in the data by performing a decoding operation on the data using cross-over bits parity data based on cross-over bits and computing a cross-over bits parity syndrome, wherein the error in the data is located at a particular intersection of column codewords and row codewords; and
performing an XOR operation on the cross-over bits parity syndrome and the cross-over bits in response to a syndrome of the decoding operation being non-zero and errors associated with an 11 stall pattern.

### Claim 14 (depends on 13)

The method of claim 13, wherein the method includes computing the cross-over bits parity syndrome as the data is read from an array of memory cells.

### Claim 15 (depends on 14)

The method of claim 14, wherein the method includes updating the cross-over bits parity syndrome based on errors that are corrected during an iterative product code decoding operation.

### Claim 16 (depends on 15)

The method of claim 15, wherein the method includes determining that a particular column codeword and a particular row codeword each have non-zero syndromes during the iterative product code decoding operation.

### Claim 17 (depends on 16)

The method of claim 16, wherein the method includes updating the cross-over bits data associated with an intersection of the particular column codeword and the particular row codeword based on a number of non-zero bits in the cross-over bits parity syndrome.

### Claim 18

An apparatus, comprising:
a memory device;
a controller coupled to the memory device configured to:
write data to a memory device, wherein the controller is configured to:
encode data with a first encoder;
create cross-over bits parity data based on cross-over bits located at intersections of column codewords and row codewords created with the first encoder; and
encode the data with a second encoder to create block-wise concatenated column codewords and row codewords; and
read the data from the memory device, wherein the controller is configured to correct errors in the data by performing a decoding operation on the data using the cross-over bits parity data and compute a cross-over bits parity syndrome as the data is read from the memory device; and
perform an XOR operation on the cross-over bits parity syndrome and the cross-over bits in response to a syndrome of the decoding operation being non-zero and errors associated with an 11 stall pattern.

### Claim 19 (depends on 18)

The apparatus of claim 18, wherein cross-over bits parity data is created by performing an XOR operation on each of the cross-over bits located at the intersections of the block-wise concatenated column codewords and row codewords.

### Claim 20 (depends on 18)

The apparatus of claim 18, wherein first encoder and the second encoder are BCH encoders.

### Claim 21 (depends on 18)

The apparatus of claim 18, wherein the encoded data includes user data, column codeword parity data, row codeword parity data, first encoder parity data, and cross-over parity data.

### Claim 22 (depends on 18)

The apparatus of claim 18, wherein the controller is configured to correct an error in the data using the cross-over bits parity data, wherein the error in the data is located at a particular intersection of the block-wise concatenated column codewords and row codewords.

### Claim 23 (depends on 18)

The apparatus of claim 18, wherein the controller is configured to correct an error in the data using the cross-over bits parity data based on a particular column codeword and a particular row codeword having a non-zero syndrome during an iterative product code decoding operation.

### Claim 24

An apparatus, comprising:
a memory device;
a controller coupled to the memory device configured to:
read data from the memory device to correct an error in the data by performing a decoding operation using cross-over bits parity data based on cross-over bits and computing a cross-over bits parity syndrome, wherein the error in the data is located at a particular intersection of column codewords and row codewords; and
perform an XOR operation on the cross-over bits parity syndrome and the cross over-bits in response to the cross-over bits parity syndrome being non-zero and errors being associated with an 11 stall pattern.

### Claim 25 (depends on 24)

The apparatus of claim 24, wherein the controller is configured to compute the cross-over bits parity syndrome as the data is read from an array of memory cells.

### Claim 26 (depends on 24)

The apparatus of claim 24, wherein the controller is configured to update the cross-over bits based on errors that are corrected during an iterative product code decoding operation.

### Claim 27 (depends on 24)

The apparatus of claim 24, wherein the controller is configured to determine that a particular column codeword and a particular row codeword has a non-zero syndrome during the iterative product code decoding operation.

### Claim 28 (depends on 27)

The apparatus of claim 27, wherein the controller is configured to update the cross-over parity syndrome based on errors that are corrected during the iterative product code decoding operation in response to determining that the particular column codeword and the particular row codeword has the non-zero syndrome.

### Claim 29 (depends on 28)

The apparatus of claim 28, wherein the controller is configured to update the cross-over bits data associated with an intersection of the particular column codeword and the particular row codeword based on a number of non-zero bits in a cross-over bits parity syndrome.

### Claim 30 (depends on 29)

The apparatus of claim 29, wherein the controller is configured to perform an XOR operation on the cross-over bits parity syndrome and the cross-over bits data associated with the intersection of the particular column codeword and the particular row codeword in response to a syndrome of the decoding operation being non-zero.