# US 10,312,934 B2 · Current source and digital to analog converter

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- Number: US 10,312,934 B2
- Document ID: US10312934B2
- Status: Granted
- Kind: B2
- Application number: 15/817,830
- Filed: 2017-11-20
- Published: 2018-05-24
- Granted: 2019-06-04
- Earliest claimed: 2016-11-23
- Assignees: Semiconductor Manufacturing International (Beijing) Corporation; Semiconductor Manufacturing International (Shanghai) Corporation
- Applicants: Semiconductor Manufacturing International (Beijing) Corporation; Semiconductor Manufacturing International (Shanghai) Corporation
- Inventors: Chunpeng Chen
- Web page: https://patentgrep.com/patent/US10312934B2

## CPC

- H03M 1/742: {using current sources as quantisation value generators}
- G05F 3/24: wherein the transistors are of the field-effect type only (G05F3/205, G05F3/26, G05F3/30 take precedence)
- G05F 3/262: {using field-effect transistors only}
- H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C)
- G05F: SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES

## Abstract

The present disclosure relates to the technical field of semiconductors, and discloses a current source and a digital to analog convertor. The current source includes a current output circuit and an impedance gain circuit which is configured to increase output impedance of the current output circuit. The current output circuit includes a first PMOS transistor and a second PMOS transistor. The impedance gain circuit includes a first end, a second end, a third end which is connected to a supply voltage, and a fourth end which is connected to the ground. A source electrode of the first PMOS transistor is connected to the supply voltage, a drain electrode of the first PMOS transistor is connected to a source electrode of the second PMOS transistor and the first end of the impedance gain circuit, and a gate electrode of the first PMOS transistor is controlled by a first bias voltage. A gate electrode of the second PMOS transistor is connected to the second end of the impedance gain circuit, and a drain electrode of the second PMOS transistor serves as an output end of the current source.

## Claims

### Claim 1

A current source, comprising:
a current output circuit, comprising:
a first PMOS transistor; and
a second PMOS transistor;
an impedance gain circuit, configured to increase output impedance of the current output circuit, the impedance gain circuit comprising:
a first end;
a second end;
a third end which is connected to a supply voltage;
a fourth end which is connected to a ground;
a third PMOS transistor;
a fourth PMOS transistor;
several PMOS transistors which are connected in series; and
a pull-up electric potential module;
wherein a source electrode of the first PMOS transistor is connected to the supply voltage, a drain electrode of the first PMOS transistor is connected to a source electrode of the second PMOS transistor and the first end of the impedance gain circuit, and a gate electrode of the first PMOS transistor is controlled by a first bias voltage;
wherein a gate electrode of the second PMOS transistor is connected to the second end of the impedance gain circuit, and a drain electrode of the second PMOS transistor serves as an output end of the current source;
wherein a gate electrode of the third PMOS transistor is connected to the first end of the impedance gain circuit, a source electrode of the third PMOS transistor is connected to the third end of the impedance gain circuit, and a drain electrode of the third PMOS transistor is connected to a source electrode of the fourth PMOS transistor by using the several PMOS transistors which are connected in series;
wherein a drain electrode of the fourth PMOS transistor is connected to the second end of the impedance gain circuit, and a gate electrode of the fourth PMOS transistor is controlled by a second bias voltage; and
wherein one end of the pull-up electric potential module is connected to the second end of the impedance gain circuit, and another end of the pull-up electric potential module is connected to the fourth end of the impedance gain circuit.

### Claim 2 (depends on 1)

The current source of claim 1, wherein the first PMOS transistor, the second PMOS transistor, the third PMOS transistor, and the fourth PMOS transistor operate in a saturation region.

### Claim 3 (depends on 1)

The current source of claim 1, wherein the pull-up electric potential module comprises a resistor or an MOS transistor.

### Claim 4 (depends on 3)

The current source of claim 3, wherein the MOS transistor comprises a NMOS transistor, a drain electrode of the NMOS transistor is connected to the second end of the impedance gain circuit, and a source electrode of the NMOS transistor is connected to the fourth end of the impedance gain circuit.

### Claim 5 (depends on 3)

The current source of claim 3, wherein the MOS transistor comprises a PMOS transistor, a source electrode of the PMOS transistor is connected to the second end of the impedance gain circuit, and a drain electrode of the PMOS transistor is connected to the fourth end of the impedance gain circuit.

### Claim 6 (depends on 1)

A digital to analog convertor, comprising: a plurality of current sources according to claim 1.

### Claim 7 (depends on 6)

The digital to analog convertor according to claim 6, further comprising:
a first switch and a second switch connected to an output end of the current source, wherein one switch of the first switch or the second switch is turned on, and the other switch of the first switch or the second switch is turned off.

### Claim 8 (depends on 7)

The digital to analog convertor of claim 7, wherein the first switch and the second switch comprise PMOS transistors.