# US 10,312,931 B2 · Programmable gain amplifier and a delta sigma analog-to-digital converter containing the PGA > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,312,931 B2 - Document ID: US10312931B2 - Status: Granted - Kind: B2 - Application number: 15/877,098 - Filed: 2018-01-22 - Published: 2019-03-21 - Granted: 2019-06-04 - Earliest claimed: 2017-09-21 - Assignees: Texas Instruments Incorporated - Applicants: Texas Instruments Incorporated - Inventors: Jun Zhang - Web page: https://patentgrep.com/patent/US10312931B2 ## CPC - H03M 1/185: {the determination of the range being based on more than one digital output value, e.g. on a running average, a power estimation or the rate of change} - H03F 1/38: Positive-feedback circuit arrangements without negative feedback - H03F 3/45475: {using IC blocks as the active amplifying circuit} - H03G 1/0088: {using discontinuously variable devices, e.g. switch-operated} - H03G 3/001: {Digital control of analog signals} - H03G 3/20: Automatic control ({H03G3/005 takes precedence;} combined with volume compression or expansion H03G7/00) - H03M 1/187: {using an auxiliary analogue/digital converter} - H03M 3/356: {Offset or drift compensation (removal of offset already present on the analogue input signal H03M3/494)} - H03M 3/464: {Details of the digital/analogue conversion in the feedback path} - H03F 2203/45522: the FBC comprising one or more potentiometers - H03M 3/494: {Sampling or signal conditioning arrangements specially adapted for delta-sigma type analogue/digital conversion systems} - H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C) - H03F: AMPLIFIERS - H03G: CONTROL OF AMPLIFICATION ## Abstract A programmable gain amplifier includes an operational amplifier and a resistor network coupled to the output node of the operational amplifier. The resistor network includes a first plurality of resistors coupled in series between the output node and a first network node. A second plurality of resistors is coupled in series between the first network node and a second network node. A unit resistor is coupled in parallel with the second plurality of resistors between the first and second resistor network nodes and a third plurality of resistors is coupled in parallel between the second resistor network node and a reference voltage. Each resistor of the second and third pluralities of resistors comprises a unit resistor. The third plurality of resistors contains N resistors and the second plurality of resistors contains (N−1) resistors. ## Claims ### Claim 1 A programmable gain amplifier (PGA) comprising: a first operational amplifier comprising a first non-inverting input node, a first inverting input node and a first output node; and a first resistor network coupled to the first output node, the first resistor network comprising: a first plurality of resistors coupled in series between the first output node and a first resistor network node; a second plurality of resistors coupled in series between the first resistor network node and a second resistor network node; a first unit resistor coupled in parallel with the second plurality of resistors between the first resistor network node and the second resistor network node; and a third plurality of resistors coupled in parallel between the second resistor network node and a reference voltage, wherein each resistor of the second plurality of resistors and of the third plurality of resistors comprises a unit resistor and further wherein the third plurality of resistors contains a number N of resistors and the second plurality of resistors contains (N−1) resistors. ### Claim 2 (depends on 1) The PGA as recited in claim 1 further comprising: a first plurality of switches, coupled before and after each of the first plurality of resistors, from which a first feedback voltage can be selected; and a second plurality of switches, coupled after ones of the second plurality of resistors, from which the first feedback voltage can be selected. ### Claim 3 (depends on 1) The PGA as recited in claim 1 further comprising: a second operational amplifier comprising a second non-inverting input node, a second inverting input node and a second output node; and a second resistor network coupled to the second output node, the second resistor network comprising: a fourth plurality of resistors coupled in series between the second output node and a fourth resistor network node; a fifth plurality of resistors coupled in series between the fourth resistor network node and a fifth resistor network node; a second unit resistor coupled in parallel with the fifth plurality of resistors between the fourth resistor network node and the fifth resistor network node; and a sixth plurality of resistors coupled in parallel between the fifth resistor network node and the reference voltage, wherein each resistor of the fifth plurality of resistors and of the sixth plurality of resistors comprises a unit resistor and further wherein the sixth plurality of resistors contains N resistors and the fifth plurality of resistors contains (N−1) resistors. ### Claim 4 (depends on 3) The PGA as recited in claim 3 further comprising: a first plurality of switches, coupled before and after each of the first plurality of resistors, from which a first feedback voltage can be selected; and a second plurality of switches, coupled after ones of the second plurality of resistors, from which the first feedback voltage can be selected; a third plurality of switches, coupled before and after each of the fourth plurality of resistors, from which a second feedback voltage can be selected; and a fourth plurality of switches, coupled after ones of the fifth plurality of resistors, from which the second feedback voltage can be selected. ### Claim 5 (depends on 2) The PGA as recited in claim 2 wherein the first resistor network is coupled between the first output node and the first inverting input node to provide the first feedback voltage. ### Claim 6 (depends on 4) The PGA as recited in claim 4 wherein the first resistor network is coupled between the first output node and the first inverting input node to provide the first feedback voltage and the second resistor network is coupled between the second output node and the second inverting input node to provide the second feedback voltage. ### Claim 7 (depends on 2) The PGA as recited in claim 2 further comprising a second operational amplifier that comprises a second non-inverting input node, a second inverting input node and a second output node, wherein the first resistor network is coupled between the first output node and the second output node. ### Claim 8 (depends on 4) The PGA as recited in claim 4 wherein the first non-inverting input node and the second non-inverting input node are each coupled to receive one of a differential pair of signals. ### Claim 9 (depends on 8) The PGA as recited in claim 8 wherein the first output node is coupled to the first inverting input to provide the first feedback voltage and the second output node is coupled to the second inverting input to provide the second feedback voltage. ### Claim 10 An electronic device comprising: a first operational amplifier having a first inverting input node and a first non-inverting input node and being further coupled to provide a first output signal on a first output node; a second operational amplifier having a second inverting input node and a second non-inverting input node and being further coupled to provide a second output signal on a second output node, each of the first and second operational amplifiers being coupled to receive a respective one of a pair of differential signals on a respective non-inverting input; and a resistor network having a first terminal coupled to the first output node and a second terminal coupled to the second output node, the resistor network comprising a first plurality of resistors coupled in series between the first output node and a first resistor network node; a second plurality of resistors coupled in series between the first resistor network node and a second resistor network node; a first unit resistor coupled in parallel with the second plurality of resistors between the first resistor network node and the second resistor network node; and a third plurality of resistors coupled in parallel between the second resistor network node and a reference voltage. ### Claim 11 (depends on 10) The electronic device as recited in claim 10 wherein the electronic device is a programmable gain amplifier coupled to provide the first and second output signals to an analog-to-digital converter (ADC). ### Claim 12 (depends on 11) The electronic device as recited in claim 11 further comprising: a first feedback loop coupled between the first output node and the first inverting input node, the first feedback loop having a first resistance; and a second feedback loop coupled between the second output node and the second inverting input node, the second feedback loop having a second resistance. ### Claim 13 (depends on 10) The electronic device as recited in claim 10 wherein the electronic device is an instrumentation amplifier, the instrumentation amplifier further comprising a third operational amplifier coupled to receive the first output signal on a third inverting input node and to receive the second output signal on a third non-inverting input node and further coupled to provide a third output signal on a third output node. ### Claim 14 (depends on 13) The electronic device as recited in claim 13 further comprising: a first feedback loop coupled between the first output node and the first inverting input node, the first feedback loop having a first resistance; a second feedback loop coupled between the second output node and the second inverting input node, the second feedback loop having a second resistance; a third feedback loop coupled between the third output node and the third inverting input node, the third feedback loop having a third resistance. ### Claim 15 (depends on 10) The electronic device as recited in claim 10 further comprising: a first plurality of switches, coupled before and after each of the first plurality of resistors, from which a feedback voltage can be selected; and a second plurality of switches, coupled after ones of the second plurality of resistors, from which the feedback voltage can be selected.