# US 10,312,930 B1 · ADC digital gain error compensation > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,312,930 B1 - Document ID: US10312930B1 - Status: Granted - Kind: B1 - Application number: 15/880,010 - Filed: 2018-01-25 - Granted: 2019-06-04 - Earliest claimed: 2018-01-25 - Assignees: Analog Devices Global Unlimited Company - Applicants: Analog Devices Global Unlimited Company - Inventors: Eamonn J. Byrne; Jesus Bonache; Andrejs Tunkels - Web page: https://patentgrep.com/patent/US10312930B1 ## CPC - H03M 1/183: {the feedback signal controlling the gain of an amplifier or attenuator preceding the analogue/digital converter} - H03F 3/2175: {using analogue-digital or digital-analogue conversion (H03F3/2173 takes precedence)} - H03F 3/45475: {using IC blocks as the active amplifying circuit} - H03M 1/06: Continuously compensating for, or preventing, undesired influence of physical parameters (periodically, {e.g. by using stored correction values,} H03M1/10) - H03M 1/186: {in feedforward mode, i.e. by determining the range to be selected directly from the input signal} - H03F 2203/45522: the FBC comprising one or more potentiometers - H03F 2203/45594: the IC comprising one or more resistors, which are not biasing resistor - H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C) - H03F: AMPLIFIERS ## Abstract Techniques are provided for compensating gain of a combined amplifier and analog-to-digital converter (ADC) circuit, for example, due to additional filtering added to an input of the circuit. In an example, an integrated circuit including an amplifier and ADC can include an amplifier circuit configured to receive an input signal and to amplify the input signal based on an input resistance and a feedback resistance, and to provide an amplified representation of the input signal, and an ADC circuit configured to receive an output of the amplifier, to determine a digital coefficient associated with an additional input resistance coupled to the amplifier, and to provide a compensated digital representation of the amplified representation of the input signal using the digital compensation coefficient. ## Claims ### Claim 1 An integrated circuit for compensating a gain error associated with an analog-to-digital converter (ADC), the integrated circuit comprising: an amplifier circuit configured to receive an input signal and to amplify the input signal based on an input resistance and a feedback resistance, and to provide an amplified representation of the input signal; and an ADC circuit configured to receive an output of the amplifier, to determine a digital coefficient associated with an additional input resistance coupled to the amplifier, and to provide a compensated digital representation of the amplified representation of the input signal using the digital compensation coefficient. ### Claim 2 (depends on 1) The integrated circuit of claim 1, including a memory location indicative of an input resistance of the amplifier circuit. ### Claim 3 (depends on 1) The integrated circuit of claim 1, wherein the amplifier circuit includes: an amplifier; an input resistor configured to couple the input signal to an input of the amplifier; an adjustable feedback resistor coupled between an output of the amplifier and the input to the amplifier. ### Claim 4 (depends on 1) The integrated circuit of claim 1, including a first register configured to store an indication of the additional input resistance. ### Claim 5 (depends on 4) The integrated circuit of claim 4, including a second register configured to store a setting for the feedback resistance. ### Claim 6 (depends on 5) The integrated circuit of claim 5, wherein the second register is a user-programmable register. ### Claim 7 (depends on 4) The integrated circuit of claim 4, wherein the ADC circuit includes a digital processing circuit configured to retrieve a first value of the first register, a second value of the memory location and to determine the digital coefficient. ### Claim 8 (depends on 7) The integrated circuit of claim 7, wherein the digital processing circuit is configured to digitally apply the digital coefficient to provide the compensated digital representation of the amplified representation of the input signal. ### Claim 9 (depends on 7) The integrated circuit of claim 7, wherein the ADC circuit includes the ADC; and wherein the digital processing circuit is configured to digitally multiply the digital coefficient with an output of the ADC to provide the compensated digital representation of the amplified representation of the input signal. ### Claim 10 (depends on 1) The integrated circuit of claim 1, including a first port configured to receive a setting for the feedback resistance. ### Claim 11 (depends on 10) The integrated circuit of claim 10, including a second port configured to receive user input indicative of the additional input resistance. ### Claim 12 A method for compensating gain error of an analog-to-digital converter (ADC) circuit, the method comprising: receiving an indication of an external resistance coupled to an input of a combined amplifier and ADC integrated circuit; amplifying a received input signal of the combined amplifier and ADC integrated circuit; converting the amplified signal to an uncompensated digital signal; determining a compensation coefficient using the indication and a stored indication of an input resistance of the combined amplifier and ADC integrated circuit; and digitally multiplying the compensation coefficient with the uncompensated digital signal to provide an output of the combined amplifier and ADC integrated circuit. ### Claim 13 (depends on 12) The method of claim 12, including receiving a setting for a feedback resistance of an amplifier of the combined amplifier and ACD integrated circuit via a port of the combined amplifier and ACD integrated circuit. ### Claim 14 (depends on 13) The method of claim 13, including adjusting a switch to provide the feedback resistance associated with the setting. ### Claim 15 (depends on 12) The method of claim 12, wherein determining the compensation coefficient includes retrieving the indication of the external resistance from a first register and retrieving the stored indication of the input resistance from a second register. ### Claim 16 (depends on 15) The method of claim 15, wherein determining the compensation coefficient includes dividing a sum of the input resistance and the external resistance by the internal resistance. ### Claim 17 A data acquisition system comprising: an electrical apparatus; an integrated analog-to-digital converter (ADC) circuit configured to receive a signal from the electrical apparatus and provide a digital representation of the signal; and wherein the integrated ADC circuit includes: an amplifier circuit configured to receive an input signal and to amplify the input signal based on an input resistance of the amplifier and a feedback resistance, and to provide an amplified representation of the input signal; and an ADC circuit configured to receive an output of the amplifier, to determine a compensation coefficient associated with an additional input resistance coupled to the amplifier, and to provide a compensated digital representation of the amplified representation of the input signal using the compensation coefficient. ### Claim 18 (depends on 17) The data acquisition system of claim 17, including: a first register configured to store an indication of the input resistance of the amplifier; a second register configured to store a setting for the additional input resistance; wherein the ADC circuit includes a digital processing circuit configured to retrieve a first value of the first register, a second value of the second register and to determine the compensation coefficient. ### Claim 19 (depends on 18) The data acquisition system of claim 18, wherein the ADC circuit includes an ADC; wherein the digital processing circuit is configured to digitally multiply the compensation coefficient with an output of the ADC to provide the compensated digital representation of the amplified representation of the input signal; and wherein the compensation coefficient is equal to a sum divided by the first value, wherein the sum is equal to an addition of the first value with the second value. ### Claim 20 (depends on 17) The data acquisition system of claim 17, wherein the electrical apparatus includes a power generation and distribution sensor.