# US 10,312,929 B1 · Analog-to-digital conversion with sampling capacitor pre-charging

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- Number: US 10,312,929 B1
- Document ID: US10312929B1
- Status: Granted
- Kind: B1
- Application number: 15/997,525
- Filed: 2018-06-04
- Granted: 2019-06-04
- Earliest claimed: 2018-06-04
- Assignees: NXP USA, Inc.
- Applicants: NXP USA, Inc.
- Inventors: Kumar Abhishek; Srikanth Jagannathan; Shanaka Pradeep Yapa Appuhamillage Don
- Web page: https://patentgrep.com/patent/US10312929B1

## CPC

- H03M 1/1245: {Details of sampling arrangements or methods}
- G11C 27/02: Sample-and-hold arrangements (G11C27/04 takes precedence)
- H03M 1/00: Analogue/digital conversion; Digital/analogue conversion (conversion of analogue values to or from differential modulation H03M3/00)
- H03M 1/10: Calibration or testing
- H03M 1/12: Analogue/digital converters ({H03M1/001 – } H03M1/10 take precedence)
- H03M 1/802: {using capacitors, e.g. neuron-mos transistors, charge coupled devices}
- H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C)
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

The embodiments described herein provide analog-to-digital converters and methods that can reduce the likelihood of excessive voltage drop during the conversion of weakly driven signals while still providing the ability to perform an accurate analog-to-digital conversion. In general, the embodiments described herein reduce the likelihood of excessive voltage drop during the conversion of weakly driven signals by pre-charging the sampling capacitor used in the conversion. For example, the embodiments can apply the buffered input signal apply to the sampling capacitor for a first sampling cycle to pre-charge the sampling capacitor, and then directly apply the unbuffered input signal to the sampling capacitor for a second sampling cycle to final-charge the sampling capacitor. With the sampling capacitor charged using the two stage charging, a digital output corresponding to the charge of the sampling capacitor is generated.

## Claims

### Claim 1

An analog-to-digital converter (ADC), comprising:
an input configured to receive an input signal;
a buffer coupled to the input, the buffer configured to receive the input signal and generate a buffered input signal;
a pre-charge controller, the pre-charge controller configured to receive the input signal and the buffered input signal, and to selectively apply the input signal and buffered input signal to a sampling capacitor, where the pre-charge controller is configured to:
apply the buffered input signal to the sampling capacitor for a first ADC sampling cycle to pre-charge the sampling capacitor;
apply the input signal to the sampling capacitor for a second ADC sampling cycle to final-charge the sampling capacitor; and
a converter configured to generate a digital output corresponding to the final-charge of the sampling capacitor, wherein the pre-charge controller is configured to receive an end-of-sampling signal from the converter, and wherein the pre-charge controller is configured to switch between applying the buffered input signal to the sampling capacitor and applying the input signal to the sampling capacitor in response to the end-of-sampling signal.

### Claim 2 (depends on 1)

The ADC of claim 1, wherein the pre-charge controller includes a switch, the switch configured to selectively switch between the buffered input signal and the input signal.

### Claim 3 (depends on 1)

The ADC of claim 1, wherein the pre-charge controller is configured to receive a set signal configured to set the pre-charge controller in an initial state with the buffered input signal coupled to the sampling capacitor.

### Claim 4 (depends on 1)

The ADC of claim 1, wherein the buffer comprises a unity gain buffer.

### Claim 5 (depends on 1)

The ADC of claim 1, wherein the pre-charge controller is configured to directly apply the input signal to the sampling capacitor for the second ADC sampling cycle to final-charge the sampling capacitor.

### Claim 6 (depends on 1)

The ADC of claim 1, wherein the input signal comprises a weakly driven reference signal.

### Claim 7 (depends on 1)

The ADC of claim 1, wherein the ADC is formed on a semiconductor die, and wherein the input signal comprises an internal reference signal on the semiconductor die.

### Claim 8 (depends on 1)

The ADC of claim 1, wherein the input signal is a band gap reference signal.

### Claim 9 (depends on 1)

The ADC of claim 1, wherein the first ADC sampling cycle and the second ADC sampling cycle are consecutive sampling cycles in the ADC.

### Claim 10

An analog-to-digital converter (ADC), comprising:
an input configured to receive an input signal;
a unity-gain buffer coupled to the input, the buffer configured to receive the input signal and generate a buffered input signal;
a pre-charge controller, the pre-charge controller including a multiplexer, the pre-charge controller configured to receive the input signal and the buffered input signal, and to selectively apply the input signal and buffered input signal to a sampling capacitor using the multiplexer, where the pre-charge controller is configured to:
apply the buffered input signal to the sampling capacitor for a first ADC sampling cycle to pre-charge the sampling capacitor;
in response to an end-of-sampling signal after the first ADC sampling cycle, directly apply the input signal to the sampling capacitor for a second ADC sampling cycle to final-charge the sampling capacitor, where the first ADC sampling cycle and the second ADC sampling cycle are consecutive sampling cycles; and
a converter configured to generate a digital output corresponding to the final-charge of the sampling capacitor.

### Claim 11 (depends on 10)

The ADC of claim 10, wherein the pre-charge controller is configured to receive a set signal configured to set the pre-charge controller in an initial state with the buffered input signal applied to the sampling capacitor.

### Claim 12

A method of performing an analog-to-digital conversion, the method comprising:
applying an input signal to an input;
buffering the input signal to generate a buffered input signal;
applying the buffered input signal to a sampling capacitor for a first ADC sampling cycle to pre-charge the sampling capacitor;
applying the input signal to the sampling capacitor for a second ADC sampling cycle to final-charge the sampling capacitor; and
generating a digital output corresponding to the final-charge of the sampling capacitor.

### Claim 13 (depends on 12)

The method of claim 12, wherein the step of applying the buffered input signal and the step of applying input signal comprises using a switch to selectively switch between the buffered input signal and the input signal.

### Claim 14 (depends on 12)

The method of claim 12, wherein the step of applying the input signal to the input for the second ADC sampling cycle is performed in response to an end-of-sampling signal.

### Claim 15 (depends on 12)

The method of claim 12, wherein the step of buffering the input signal comprising buffering the input signal with a unity gain buffer.

### Claim 16 (depends on 12)

The method of claim 12, wherein the step of applying the input signal to the input for the second ADC sampling cycle comprises directly applying the input signal to the sampling capacitor for the second ADC sampling cycle to final-charge the sampling capacitor.

### Claim 17 (depends on 12)

The method of claim 12, wherein the input signal comprises a weakly driven reference signal.

### Claim 18 (depends on 12)

The method of claim 12, wherein the ADC is formed on a semiconductor die, and wherein the input signal comprises an internal reference signal on the semiconductor die.

### Claim 19 (depends on 12)

The method of claim 12, wherein the input signal is a band gap reference signal.