# US 10,312,928 B2 · Successive approximation register analog-to-digital converter > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,312,928 B2 - Document ID: US10312928B2 - Status: Granted - Kind: B2 - Application number: 15/983,764 - Filed: 2018-05-18 - Published: 2018-09-20 - Granted: 2019-06-04 - Earliest claimed: 2013-04-25 - Assignees: MaxLinear, Inc. - Applicants: MaxLinear, Inc. - Inventors: Kaveh Moazzami; Pawan Tiwari; Gaurav Chandra - Web page: https://patentgrep.com/patent/US10312928B2 ## CPC - H03M 1/1245: {Details of sampling arrangements or methods} - H03M 1/0836: {of phase error, e.g. jitter} - H03M 1/12: Analogue/digital converters ({H03M1/001 – } H03M1/10 take precedence) - H03M 1/46: with digital/analogue converter for supplying reference values to converter - H03M 1/468: {in which the input S/H circuit is merged with the feedback DAC array} - H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C) ## Abstract Aspects of a method and apparatus for converting an analog input value to a digital output code are provided. One embodiment of the apparatus includes a digital-to-analog converter, a comparator, and control logic circuitry. The digital-to-analog converter is configured to generate an analog reference value based on a received digital reference value. The comparator is configured to compare an analog input value to the analog reference value after expiration of an allotted settling time for the digital-to-analog converter and generate a comparison result indicative a relationship between the analog input value and the analog reference value. The control logic circuitry is configured to select the allotted settling time for the digital-to-analog converter based on a bit position of a digital output code to be determined, and update the bit position of the digital output code based on the comparison result. ## Claims ### Claim 1 A method of converting an analog input signal to a digital output code, the method comprising: allotting time to a digital-to-analog converter based on an expected voltage swing magnitude of an analog reference signal generated by the digital-to-analog converter; generating, with the digital-to-analog converter, the analog reference signal to be representative of a digital reference code; comparing the analog input signal to the analog reference signal in response to expiration of the time allotted to the digital-to-analog converter; and updating one or more bit positions of the digital output code based on said comparing. ### Claim 2 (depends on 1) The method of claim 1, wherein said allotting comprises allotting the time such that the time allotted is greater in response to the expected voltage swing magnitude having a first magnitude than in response to the expected voltage swing magnitude having a second magnitude that is less than the first magnitude. ### Claim 3 (depends on 1) The method of claim 1, wherein said allotting comprises allotting the time such that the time is increased as the expected voltage swing magnitude increases. ### Claim 4 (depends on 1) The method of claim 1, wherein said allotting comprises adjusting a time constant for an RC circuit of a timer that tracks the time allotted to the digital-to-analog converter. ### Claim 5 (depends on 1) The method of claim 1, wherein said allotting comprises adjusting an effective resistance value for an RC circuit of a timer that tracks the time allotted to the digital-to-analog converter. ### Claim 6 (depends on 1) The method of claim 1, wherein said allotting comprises selectively actuating one or more switches to short circuit one or more resistors from an RC circuit of a timer that tracks the time allotted to the digital-to-analog converter. ### Claim 7 (depends on 1) The method of claim 1, wherein said allotting comprises adjusting an effective capacitance value for an RC circuit of a timer that tracks the time allotted to the digital-to-analog converter. ### Claim 8 (depends on 1) The method of claim 1, wherein said allotting comprises selectively opening one or more switches to effectively remove one or more capacitors from an RC circuit of a timer that tracks the time allotted to the digital-to-analog converter. ### Claim 9 (depends on 1) The method of claim 1, wherein said allotting comprises adjusting a digital counter of a timer that tracks the time allotted to the digital-to-analog converter. ### Claim 10 (depends on 1) The method of claim 1, wherein: said comparing comprises comparing the analog input signal to the analog reference signal using a comparator of an analog-to-digital converter; and said updating comprises sampling a comparison output of the comparator in response to expiration of a second time allotted to the comparator, and updating the one or more bit positions of the digital output code based on the comparison output. ### Claim 11 An apparatus, comprising: a digital-to-analog converter configured to generate an analog reference signal based on a digital reference code; a timer that tracks time allotted to the digital-to-analog converter; a comparator configured to compare an analog input signal to the analog reference signal in response to expiration of the time allotted to the digital-to-analog converter; and control logic circuitry configured to allot the time to the digital-to-analog converter based on an expected voltage swing magnitude of the analog reference signal generated by the digital-to-analog converter, and update one or more bit positions of a digital output code based on a comparison output of the comparator. ### Claim 12 (depends on 11) The apparatus of claim 11, wherein the control logic circuitry is further configured to allot the time such that the time allotted is greater in response to the expected voltage swing magnitude having a first magnitude than in response to the expected voltage swing magnitude having a second magnitude that is less than the first magnitude. ### Claim 13 (depends on 11) The apparatus of claim 11, wherein the control logic circuitry is further configured to allot the time such that the time is increased as the expected voltage swing magnitude increases. ### Claim 14 (depends on 11) The apparatus of claim 11, wherein: the timer comprises an RC circuit; and the control logic circuitry is further configured to adjust the time allotted to the digital-to-analog converter by adjusting a time constant of the RC circuit. ### Claim 15 (depends on 11) The apparatus of claim 11, wherein: the timer comprises an RC circuit; and the control logic circuitry is further configured to allot the time to the digital-to-analog converter by adjusting an effective resistance value of the RC circuit. ### Claim 16 (depends on 11) The apparatus of claim 11, wherein: the timer comprises one or more switches configured to short circuit one or more resistors of an RC circuit; and the control logic circuitry is further configured to allot the time to the digital-to-analog converter by selectively actuating the one or more switches to short circuit the one or more resistors of the RC circuit. ### Claim 17 (depends on 11) The apparatus of claim 11, wherein: the timer comprises an RC circuit; and the control logic circuitry is further configured to allot the time to the digital-to-analog converter by adjusting an effective capacitance value of the RC circuit. ### Claim 18 (depends on 17) The apparatus of claim 17, wherein: the timer comprises one or more switches; and the control logic circuitry is further configured to allot the time to the digital-to-analog converter by selectively opening the one or more switches to effectively remove one or more capacitors from the RC circuit. ### Claim 19 (depends on 11) The apparatus of claim 11, wherein: the timer comprises a digital counter; and the control logic circuitry is further configured to allot the time to the digital-to-analog converter by adjusting the digital counter. ### Claim 20 (depends on 11) The apparatus of claim 11, further comprising: a second timer that tracks a second time allotted to the comparator; wherein the control log circuitry is configured to sample the comparator output in response to expiration of the second time allotted to the comparator.