# US 10,312,927 B1 · Calibration for time-interleaved analog-to-digital converters and signal generators therefor > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,312,927 B1 - Document ID: US10312927B1 - Status: Granted - Kind: B1 - Application number: 15/935,988 - Filed: 2018-03-26 - Granted: 2019-06-04 - Earliest claimed: 2018-03-26 - Assignees: QUALCOMM Incorporated - Applicants: QUALCOMM Incorporated - Inventors: Seyed Arash Mirhaj; Elias Dagher; Yongjian Tang; Dinesh Alladi; Masoud Ensafdaran; Lei Sun; Anand Meruva; Yuhua Guo; Balasubramanian Sivakumar - Web page: https://patentgrep.com/patent/US10312927B1 ## CPC - H03M 1/1033: {over the full range of the converter, e.g. for correcting differential non-linearity} - H03M 1/0624: {by synchronisation} - H03M 1/1014: {at one point of the transfer characteristic, i.e. by adjusting a single reference value, e.g. bias or gain error (gain setting for range control H03M1/18)} - H03K 4/08: having sawtooth shape - H03M 1/1215: {using time-division multiplexing} - H03M 1/46: with digital/analogue converter for supplying reference values to converter - H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C) - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) ## Abstract Certain aspects of the present disclosure provide methods and apparatus for calibrating time-interleaved analog-to-digital converter (ADC) circuits and generating a suitable signal for such calibration. Certain aspects provide a signal generator for calibrating a time-interleaved ADC circuit having a plurality of channels. The signal generator generally includes a pattern generator configured to receive a periodic signal and to output a bitstream based on the periodic signal and a conversion circuit having an input coupled to an output of the pattern generator and configured to generate a waveform based on the bitstream. The bitstream has a bit pattern with a total number of bits that shares no common factor with a number of the channels and includes a relatively lower frequency component combined with a relatively higher frequency component. ## Claims ### Claim 1 A signal generator for calibrating a time-interleaved analog-to-digital converter (ADC) circuit having a plurality of channels, comprising: a pattern generator configured to receive a periodic signal and output a bitstream based on the periodic signal, wherein the bitstream: has a bit pattern with a total number of bits that shares no common factor with a number of the channels; and includes a relatively lower frequency component combined with a relatively higher frequency component; and a conversion circuit having an input coupled to an output of the pattern generator and configured to generate a waveform based on the bitstream, wherein the signal generator is configured to output a double sawtooth signal as the waveform. ### Claim 2 (depends on 1) The signal generator of claim 1, wherein the total number of bits for one period of the double sawtooth signal is 127. ### Claim 3 (depends on 1) The signal generator of claim 1, wherein the total number of bits for one period of the double sawtooth signal is 63 and wherein the number of the channels is 8. ### Claim 4 (depends on 1) The signal generator of claim 1, wherein the bitstream for the double sawtooth signal comprises at least one of: a first repeating bit pattern of {0,1,0} for a ramping down portion of the double sawtooth signal; or a second repeating bit pattern of {1,0,1} for a ramping up portion of the double sawtooth signal. ### Claim 5 (depends on 1) The signal generator of claim 1, wherein: the pattern generator comprises a multiplexer having a plurality of inputs coupled to outputs of a plurality of waveform bitstream generating circuits and an output coupled to the output of the pattern generator; and the multiplexer is configured to select one of the outputs of the plurality of waveform bitstream generating circuits as the bitstream output by the pattern generator. ### Claim 6 (depends on 5) The signal generator of claim 5, wherein the plurality of waveform bitstream generating circuits is configured to generate at least one of a first bitstream for a double sawtooth signal, a second bitstream for a single sawtooth signal, or a third bitstream based on a linear feedback shift register (LFSR) sequence. ### Claim 7 (depends on 1) The signal generator of claim 1, wherein the pattern generator comprises a delay tuning circuit configured to variably delay the periodic signal or a version of the periodic signal. ### Claim 8 (depends on 1) The signal generator of claim 1, wherein the pattern generator comprises a frequency dividing circuit configured to divide a frequency of the periodic signal or of a version of the periodic signal to generate a lower frequency periodic signal. ### Claim 9 (depends on 1) An integrated circuit (IC) comprising the signal generator of claim 1 and the time-interleaved analog-to-digital converter circuit, wherein an output of the conversion circuit is selectively coupled to an input of the time-interleaved analog-to-digital converter circuit. ### Claim 10 (depends on 9) The integrated circuit of claim 9, wherein the signal generator and the time-interleaved analog-to-digital converter circuit receive power from a same power supply rail. ### Claim 11 (depends on 9) The integrated circuit of claim 9, wherein the periodic signal the pattern generator is configured to receive is a sampling clock signal for the time-interleaved analog-to-digital converter circuit. ### Claim 12 A method of generating a waveform for calibrating a time-interleaved analog-to-digital converter (ADC) circuit having a plurality of channels, comprising: receiving a periodic signal; generating a bitstream based on the periodic signal, wherein the bitstream: has a bit pattern with a total number of bits that shares no common factor with a number of the channels; and includes a relatively lower frequency component combined with a relatively higher frequency component; and generating the waveform based on the bitstream, wherein the waveform comprises a double sawtooth signal. ### Claim 13 (depends on 12) The method of claim 12, wherein the total number of bits for one period of the double sawtooth signal is 127. ### Claim 14 (depends on 12) The method of claim 12, wherein the total number of bits for one period of the double sawtooth signal is 63 and wherein the number of the channels is 8. ### Claim 15 (depends on 12) The method of claim 12, wherein the bitstream for the double sawtooth signal comprises at least one of: a first repeating bit pattern of {0,1,0} for a ramping down portion of the double sawtooth signal; or a second repeating bit pattern of {1,0,1} for a ramping up portion of the double sawtooth signal. ### Claim 16 (depends on 12) The method of claim 12, wherein generating the bitstream comprises selecting one of a plurality of different bitstreams as the bitstream. ### Claim 17 (depends on 16) The method of claim 16, wherein the plurality of different bitstreams comprises at least one of a first bitstream for a double sawtooth signal, a second bitstream for a single sawtooth signal, or a third bitstream based on a linear feedback shift register (LFSR) sequence. ### Claim 18 (depends on 12) The method of claim 12, wherein generating the bitstream comprises variably delaying the periodic signal or a version of the periodic signal. ### Claim 19 (depends on 12) The method of claim 12, wherein generating the bitstream comprises dividing a frequency of the periodic signal or of a version of the periodic signal to generate a lower frequency periodic signal. ### Claim 20 (depends on 12) The method of claim 12, wherein the periodic signal comprises a sampling clock signal for the time-interleaved analog-to-digital converter circuit. ### Claim 21 An apparatus for generating an analog waveform for calibrating a time-interleaved analog-to-digital converter (ADC) circuit having a plurality of channels, the apparatus comprising: means for generating a digital bitstream based on a periodic signal, wherein the digital bitstream: has a bit pattern with a total number of bits that shares no common factor with a number of the channels; and includes a relatively lower frequency component combined with a relatively higher frequency component; and means for generating the analog waveform based on the bitstream, wherein the analog waveform comprises a double sawtooth signal.