# US 10,312,925 B1 · Multiplying DAC of pipelined ADC > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,312,925 B1 - Document ID: US10312925B1 - Status: Granted - Kind: B1 - Application number: 16/105,142 - Filed: 2018-08-20 - Published: 2019-05-30 - Granted: 2019-06-04 - Earliest claimed: 2017-11-28 - Assignees: Realtek Semiconductor Corp. - Applicants: Realtek Semiconductor Corporation - Inventors: Chih-Lung Chen; Ying-Cheng Wu; Shih-Hsiung Huang - Web page: https://patentgrep.com/patent/US10312925B1 ## CPC - H03M 1/001: {Analogue/digital/analogue conversion} - H03F 3/45475: {using IC blocks as the active amplifying circuit} - H03M 1/164: {the steps being performed sequentially in series-connected stages (H03M1/161 takes precedence)} - H03F 2200/129: there being a feedback over the complete amplifier - H03F 2203/45116: Feedback coupled to the input of the differential amplifier - H03F 2203/45544: the IC comprising one or more capacitors, e.g. coupling capacitors - H03F 2203/45551: the IC comprising one or more switched capacitors - H03M 1/42: Sequential comparisons in series-connected stages with no change in value of analogue signal - H03M 1/44: Sequential comparisons in series-connected stages with change in value of analogue signal - H03M 1/442: {using switched capacitors} - H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C) - H03F: AMPLIFIERS ## Abstract This invention discloses a multiplying digital-to-analog converter (MDAC) applied to a pipelined analog-to-digital converter (pipelined ADC). The MDAC includes an operational amplifier. The MDAC samples a differential input signal in a sampling phase and performs subtraction and multiplication operations in an amplification phase according to a first reference voltage and a second reference voltage. The common-mode voltage of the first reference voltage and the second reference voltage is not substantially equal to the common-mode voltage of the differential input signal; and/or the voltage difference between the first reference voltage and the second reference voltage is not substantially equal to one half of an allowed maximum peak-to-peak value of the differential input signal. One of the first reference voltage and the second reference voltage can be ground. ## Claims ### Claim 1 A multiplying digital-to-analog converter (MDAC) applied to a pipelined analog-to-digital converter (ADC) and operating in a sampling phase or an amplification phase, comprising: an operational amplifier; a first capacitor having a first end and a second end, wherein the first end is coupled to a first reference voltage in the sampling phase and coupled to a first input terminal of the operational amplifier but not to the first reference voltage in the amplification phase, wherein the second end receives a differential input signal in the sampling phase and is coupled to a first output terminal of the operational amplifier in the amplification phase; a second capacitor having a third end and a fourth end, wherein the third end is coupled to the first reference voltage in the sampling phase and coupled to the first input terminal of the operational amplifier but not to the first reference voltage in the amplification phase, wherein the fourth end receives the differential input signal in the sampling phase and is coupled to a second reference voltage in the amplification phase; a third capacitor having a fifth end and a sixth end, wherein the fifth end is coupled to the first reference voltage in the sampling phase and coupled to a second input terminal of the operational amplifier but not to the first reference voltage in the amplification phase, wherein the sixth end receives the differential input signal in the sampling phase and is coupled to a second output terminal of the operational amplifier in the amplification phase; and a fourth capacitor having a seventh end and an eighth end, wherein the seventh end is coupled to the first reference voltage in the sampling phase and coupled to the second input terminal of the operational amplifier but not to the first reference voltage in the amplification phase, wherein the eighth end receives the differential input signal in the sampling phase and is coupled to a third reference voltage in the amplification phase; wherein one of the second reference voltage and the third reference voltage is substantially ground. ### Claim 2 (depends on 1) The MDAC of claim 1, wherein the DC voltages of the first and second input terminals of the operational amplifier in the amplification phase are not substantially equal to the first reference voltage. ### Claim 3 (depends on 2) The MDAC of claim 2, wherein the common-mode voltage of the differential input signal is a first voltage, the common-mode voltage of the second reference voltage and the third reference voltage is a second voltage, and a difference between the first reference voltage and the DC voltage of the first or second input terminal of the operational amplifiers in the amplification phase is substantially equal to (N−1)/N times the difference between the first voltage and the second voltage, and N is a positive integer. ### Claim 4 (depends on 3) The MDAC of claim 3, wherein N is equal to 2P, and P is the integer part of the number of bits of the pipelined ADC. ### Claim 5 (depends on 1) The MDAC of claim 1 further comprising: a fifth capacitor having a ninth end and a tenth end, wherein the ninth end is coupled to the first reference voltage in the sampling phase and coupled to the first input terminal of the operational amplifier but not to the first reference voltage in the amplification phase, wherein the tenth end receives the differential input signal in the sampling phase and is coupled to a common-mode voltage of the second reference voltage and the third reference voltage in the amplification phase; and a sixth capacitor having an eleventh end and a twelfth end, wherein the eleventh end is coupled to the first reference voltage in the sampling phase, and is coupled to the second input terminal of the operational amplifier but not to the first reference voltage in the amplification phase, wherein the twelfth end receives the differential input signal in the sampling phase and is coupled to the common-mode voltage in the amplification phase. ### Claim 6 (depends on 5) The MDAC of claim 5, wherein the capacitance value of the second capacitor is X times the capacitance value of the first capacitor, the capacitance value of the fifth capacitor is Y times the capacitance value of the first capacitor, and the sum of X and Y is substantially one. ### Claim 7 (depends on 6) The MDAC of claim 6, wherein the difference between the second reference voltage and the third reference voltage is a first voltage difference, and when the first voltage difference is substantially R times an allowed maximum peak-to-peak value of the differential input signal, X is equal to ½R, R being a positive number. ### Claim 8 (depends on 5) The MDAC of claim 5, wherein the difference between the second reference voltage and the third reference voltage is not substantially equal to half of an allowed maximum peak-to-peak value of the differential input signal. ### Claim 9 A multiplying digital-to-analog converter (MDAC) applied to a pipelined analog-to-digital converter (ADC) and operating in a sampling phase or an amplification phase, comprising: an operational amplifier a first capacitor having a first end and a second end, wherein the first end is coupled to a first reference voltage in the sampling phase and coupled to a first input terminal of the operational amplifier but not to the first reference voltage in the amplification phase, wherein the second end receives a differential input signal in the sampling phase and is coupled to a first output terminal of the operational amplifier in the amplification phase; a second capacitor having a third end and a fourth end, wherein the third end is coupled to the first reference voltage in the sampling phase and coupled to the first input terminal of the operational amplifier but not to the first reference voltage in the amplification phase, wherein the fourth end receives the differential input signal in the sampling phase and is coupled to a second reference voltage in the amplification phase; a third capacitor having a fifth end and a sixth end, wherein the fifth end is coupled to the first reference voltage in the sampling phase and coupled to a second input terminal of the operational amplifier but not to the first reference voltage in the amplification phase, wherein the sixth end receives the differential input signal in the sampling phase and is coupled to a second output terminal of the operational amplifier in the amplification phase; and a fourth capacitor having a seventh end and an eighth end, wherein the seventh end is coupled to the first reference voltage in the sampling phase and coupled to the second input terminal of the operational amplifier but not to the first reference voltage in the amplification phase, wherein the eighth end receives the differential input signal in the sampling phase and is coupled to a third reference voltage in the amplification phase; wherein the DC voltages of the first and second input terminals of the operational amplifier in the amplification phase are not substantially equal to the first reference voltage. ### Claim 10 (depends on 9) The MDAC of claim 9, wherein the common-mode voltage of the differential input signal is a first voltage, the common-mode voltage of the second reference voltage and the third reference voltage is a second voltage, and a difference between the first reference voltage and the DC voltage of the first or second input terminal of the operational amplifiers in the amplification phase is substantially equal to (N−1)/N times the difference between the first voltage and the second voltage, and N is a positive integer. ### Claim 11 (depends on 10) The MDAC of claim 10, wherein N is equal to 2P, and P is the integer part of the number of bits of the pipelined ADC. ### Claim 12 A multiplying digital-to-analog converter (MDAC) applied to a pipelined analog-to-digital converter (ADC) and operating in a sampling phase or an amplification phase, comprising: an operational amplifier; a first capacitor having a first end and a second end, wherein the first end is coupled to a first reference voltage in the sampling phase and coupled to a first input terminal of the operational amplifier but not to the first reference voltage in the amplification phase, wherein the second end receives a differential input signal in the sampling phase and is coupled to a first output terminal of the operational amplifier in the amplification phase; a second capacitor having a third end and a fourth end, wherein the third end is coupled to the first reference voltage in the sampling phase and coupled to the first input terminal of the operational amplifier but not to the first reference voltage in the amplification phase, wherein the fourth end receives the differential input signal in the sampling phase and is coupled to a second reference voltage in the amplification phase; a third capacitor having a fifth end and a sixth end, wherein the fifth end is coupled to the first reference voltage in the sampling phase and coupled to a second input terminal of the operational amplifier but not to the first reference voltage in the amplification phase, wherein the sixth end receives the differential input signal in the sampling phase and is coupled to a second output terminal of the operational amplifier in the amplification phase; a fourth capacitor having a seventh end and an eighth end, wherein the seventh end is coupled to the first reference voltage in the sampling phase and coupled to the second input terminal of the operational amplifier but not to the first reference voltage in the amplification phase, wherein the eighth end receives the differential input signal in the sampling phase and is coupled to a third reference voltage in the amplification phase; a fifth capacitor having a ninth end and a tenth end, wherein the ninth end is coupled to the first reference voltage in the sampling phase and coupled to the first input terminal of the operational amplifier but not to the first reference voltage in the amplification phase, wherein the tenth end receives the differential input signal in the sampling phase and is coupled to a common-mode voltage of the second reference voltage and the third reference voltage in the amplification phase; and a sixth capacitor having an eleventh end and a twelfth end, wherein the eleventh end is coupled to the first reference voltage in the sampling phase, and is coupled to the second input terminal of the operational amplifier but not to the first reference voltage in the amplification phase, wherein the twelfth end receives the differential input signal in the sampling phase and is coupled to the common-mode voltage in the amplification phase. ### Claim 13 (depends on 12) The MDAC of claim 12, wherein the capacitance value of the second capacitor is X times the capacitance value of the first capacitor, the capacitance value of the fifth capacitor is Y times the capacitance value of the first capacitor, and the sum of X and Y is substantially one. ### Claim 14 (depends on 13) The MDAC of claim 13, wherein the difference between the second reference voltage and the third reference voltage is a first voltage difference, and when the first voltage difference is substantially R times an allowed maximum peak-to-peak value of the differential input signal, X is equal to ½R, R being a positive number. ### Claim 15 (depends on 12) The MDAC of claim 12, wherein the difference between the second reference voltage and the third reference voltage is not substantially equal to half of an allowed maximum peak-to-peak value of the differential input signal.