# US 10,312,923 B2 · Electronic circuit, phase-locked loop, transceiver circuit, radio station and method of frequency dividing

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- Number: US 10,312,923 B2
- Document ID: US10312923B2
- Status: Granted
- Kind: B2
- Application number: 16/113,332
- Filed: 2018-08-27
- Published: 2018-12-20
- Granted: 2019-06-04
- Earliest claimed: 2018-08-27
- Assignees: Telefonaktiebolaget LM Ericsson (publ)
- Applicants: Telefonaktiebolaget LM Ericsson (publ)
- Inventors: Staffan Ek; Tony Påhlsson; Henrik Sjöland
- Web page: https://patentgrep.com/patent/US10312923B2

## CPC

- H03L 7/0996: {Selecting a signal among the plurality of phase-shifted signals produced by the ring oscillator}
- H03L 7/191: using at least two different signals from the frequency divider or the counter for determining the time difference (H03L7/193, H03L7/195 take precedence)
- H03L 7/1974: {for fractional frequency division}
- H03K 23/667: {by switching the base during a counting cycle}
- H03K 23/68: with a base which is a non-integer
- H03L: AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES (generation of oscillations H03B)
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)

## Abstract

Exemplary embodiments include an electronic frequency-divider circuit comprising a multi-phase generator circuit configured to: receive an oscillating input signal having a frequency f; determine an integer divide ratio Q based on a first control signal input; and based on the oscillating input signal, generate an N-phase output signal having a frequency f-divided-by-M, wherein M is an integer and adjacent phases of the N-phase output signal are separated by 360-divided-by-(M-times-Q) degrees. The divider circuit can also include a control circuit configured to receive a control input and, based on the control input: provide the first control signal to the multi-phase generator circuit; and select a particular phase of the N-phase output signal. Exemplary embodiments also include a phase-locked loop circuits, transceiver circuits, radio stations, and methods of frequency-dividing an oscillating signal.

## Claims

### Claim 1

An electronic frequency-divider circuit comprising:
a multi-phase generator circuit configured to:
receive an oscillating input signal having a frequency f;
determine an integer divide ratio Q based on a first control signal input; and
based on the oscillating input signal, generate an N-phase output signal having a frequency f-divided-by-M, wherein M is an integer and adjacent phases of the N-phase output signal are separated by 360-divided-by-(M-times-Q) degrees;
a control circuit configured to receive a control input and, based on the control input:
provide the first control signal to the multi-phase generator circuit; and
select a particular phase of the N-phase output signal.

### Claim 2 (depends on 1)

The electronic frequency-divider circuit of claim 1, wherein the multi-phase generator circuit comprises a first frequency divider arranged to receive the oscillating input signal and generate a first N-phase signal having a frequency f-divided-by-M, wherein adjacent phases of the first N-phase signal are separated by 360-divided-by-M degrees.

### Claim 3 (depends on 2)

The electronic frequency-divider circuit of claim 2, wherein the multi-phase generator circuit further comprises:
a second frequency divider arranged to, based on the divide ratio Q, generate a second oscillating signal having a frequency f-divided-by-(M-times-Q); and
a latch circuit arranged to generate the N-phase output signal based on the second oscillating signal and the first N-phase signal.

### Claim 4 (depends on 1)

The electronic frequency-divider circuit of claim 1, wherein:
the control circuit is further arranged to generate a second control signal; and
the electronic frequency-divider circuit further comprises a multiplexer circuit configured to:
receive the N-phase output signal; and
generate an output signal, comprising the particular phase of the N-phase output signal, based on the second control signal.

### Claim 5 (depends on 4)

The electronic frequency-divider circuit of claim 4, wherein:
the control input comprises a programmable divide ratio; and
the control circuit is further arranged to generate the first control signal and the second control signal based on the programmable divide ratio.

### Claim 6 (depends on 5)

The electronic frequency-divider circuit of claim 5, wherein the control circuit comprises a state machine arranged to provide the first control signal and the second control signal, for each particular cycle of the output signal, based on the programmable divide ratio and the output signal provided by the multiplexer circuit during a cycle of the output signal that precedes the particular cycle.

### Claim 7 (depends on 4)

The electronic frequency-divider circuit of claim 4, further comprising an output latch circuit arranged to generate a further output signal based on the oscillating input signal received at a clocking input and the output signal from the multiplexer circuit received at a data input.

### Claim 8 (depends on 4)

The electronic frequency-divider circuit of claim 4, wherein:
the control input comprises a programmable divide ratio; and
the control circuit comprises:
an integer divider circuit arranged to generate an integer quotient value and an integer remainder value based on dividing the programmable divide ratio by M;
a modulo-M-counter arranged to:
receive the remainder value as an input and the output signal as a clocking input; and
output a count value and a carry value; and
an adder circuit arranged to generate the first control signal by adding the integer quotient value and the carry value.

### Claim 9 (depends on 8)

The electronic frequency-divider circuit of claim 8, wherein control circuit is further configured to generate the second control signal based on the count value.

### Claim 10 (depends on 3)

The electronic frequency-divider circuit of claim 3, wherein the second frequency divider is further arranged to generate the second oscillating signal based on a particular phase of the first N-phase signal.

### Claim 11 (depends on 1)

The electronic frequency-divider circuit of claim 1, wherein M equals N.

### Claim 12 (depends on 1)

A phase-locked loop circuit comprising the electronic frequency-divider circuit of claim 1.

### Claim 13 (depends on 12)

A transceiver circuit comprising the phase-locked loop circuit of claim 12.

### Claim 14 (depends on 13)

A radio station comprising:
the transceiver circuit of claim 13; and
an antenna arrangement connected to the transceiver circuit.

### Claim 15

A method of frequency-dividing an oscillating input signal, the method comprising:
receiving an oscillating input signal having a frequency f;
determining an integer divide ratio Q based on a control input;
based on the oscillating input signal, generating an N-phase output signal having a frequency f-divided-by-M, wherein M is an integer and adjacent phases of the N-phase output signal are separated by 360-divided-by-(M-times-Q) degrees; and
selecting a particular phase of the N-phase output signal.

### Claim 16 (depends on 15)

The method of claim 15, wherein generating the N-phase output signal comprises generating a first N-phase signal having a frequency f-divided-by-M, wherein adjacent phases of the first N-phase signal are separated by 360-divided-by-M degrees.

### Claim 17 (depends on 15)

The method of claim 15, wherein generating the N-phase output signal further comprises:
generating a second oscillating signal having a frequency f-divided-by-(M-times-Q); and
generating the N-phase output signal based on the second oscillating signal and the first N-phase signal.

### Claim 18 (depends on 15)

The method of claim 15, wherein:
the control input comprises a programmable divide ratio; and
the method further comprises generating a first control signal and a second control signal based on the programmable divide ratio.

### Claim 19 (depends on 18)

The method of claim 18, wherein selecting a particular phase of the N-phase output signal is based on the second control signal.

### Claim 20 (depends on 18)

The method of claim 18, wherein determining the integer divide ratio Q is based on the first control signal.