# US 10,312,917 B2 · Configurable computing array for implementing complex math functions > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,312,917 B2 - Document ID: US10312917B2 - Status: Granted - Kind: B2 - Application number: 16/059,023 - Filed: 2018-08-08 - Published: 2018-12-20 - Granted: 2019-06-04 - Earliest claimed: 2016-03-05 - Assignees: HangZhou HaiCun Information Technology Co., Ltd.; Guobiao Zhang - Applicants: Guobiao Zhang - Inventors: Guobiao Zhang - Web page: https://patentgrep.com/patent/US10312917B2 ## CPC - H03K 19/17728: Reconfigurable logic blocks, e.g. lookup tables - H03K 19/17736: Structural details of routing resources - H03K 19/1776: for memories - H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels - H10B 43/35: with cell select transistors, e.g. NAND - H10B 63/30: {comprising selection components having three or more electrodes, e.g. transistors} - H10B 63/84: {arranged in a direction perpendicular to the substrate, e.g. 3D cell arrays} - H10B 63/845: {the switching components being connected to a common vertical conductor} - H10W 90/00: Package configurations - H10B 20/20: Programmable ROM [PROM] devices comprising field-effect components (H10B20/10 takes precedence) - H10B 20/25: One-time programmable ROM [OTPROM] devices, e.g. using electrically-fusible links - H10W 72/823: {Interconnections through encapsulations, e.g. pillars through molded resin on a lateral side a chip} - H10W 90/22: the stacked chips being on both top and bottom sides of a package substrate, interposer or RDL - H10W 90/26: the stacked chips being of the same size without any chips being laterally offset, e.g. chip stacks having a rectangular shape - H10W 90/291: {characterised by containers, encapsulations, or other housings for the stacked chips} - H10W 90/722: {between stacked chips} - H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL} - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) - H10B: ELECTRONIC MEMORY DEVICES - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract To implement a complex math function, a configurable computing array comprises at least an array of configurable interconnects, an array of configurable logic elements and an array of configurable computing elements. Each configurable computing element comprises at least a memory for storing a look-up table (LUT) for a math function. ## Claims ### Claim 1 A configurable computing array, comprising: at least an array of configurable logic elements including a configurable logic element, wherein said configurable logic element selectively realizes a logic function from a logic library; and at least an array of configurable computing elements including first and second configurable computing elements, wherein said first configurable computing element comprises a first memory for storing a first look-up table (LUT) for a first math function; and, said second configurable computing element comprises a second memory for storing a second LUT for a second math function; whereby said configurable computing array realizes a complex math function by programming said configurable logic elements and said configurable computing elements, wherein said complex math function is a combination of at least said first and second math functions. ### Claim 2 (depends on 1) The configurable computing array according to claim 1, further comprising at least an array of configurable interconnects including a configurable interconnect, wherein said configurable interconnect selectively realizes an interconnect from an interconnect library. ### Claim 3 (depends on 1) The configurable computing array according to claim 1, wherein each of said configurable computing elements comprises a re-programmable memory, whereby each of said configurable computing elements can be re-configured to realize a different math function by loading the LUT for said different math function into said re-programmable memory. ### Claim 4 (depends on 1) The configurable computing array according to claim 1, wherein at least a first portion of said configurable logic elements and at least a second portion of said configurable computing elements are disposed on a same physical level. ### Claim 5 (depends on 1) The configurable computing array according to claim 1, wherein at least a first portion of said configurable logic elements and at least a second portion of said configurable computing elements are disposed on different physical levels. ### Claim 6 (depends on 5) The configurable computing array package according to claim 5, wherein said first and second memories comprise at least a three-dimensional memory (3D-M) array. ### Claim 7 (depends on 6) The configurable computing array according to claim 6, wherein said 3D-M array is a three-dimensional horizontal memory (3D-MH) array or a three-dimensional vertical memory (3D-MV) array. ### Claim 8 (depends on 5) The configurable computing array according to claim 5, further comprising a semiconductor substrate with first and second sides, wherein said configurable logic elements are disposed on said first side; said configurable computing elements are disposed on said second side; said configurable logic elements and said configurable computing elements are coupled by a plurality of through-substrate vias through said semiconductor substrate. ### Claim 9 (depends on 5) The configurable computing array according to claim 5, wherein said configurable logic elements are disposed on at least a configurable logic die; said configurable computing elements are disposed on at least a configurable computing die; said configurable logic die and said configurable computing die are located in a same package. ### Claim 10 (depends on 1) The configurable computing array according to claim 1, further comprising at least one multiplier. ### Claim 11 A configurable computing array, comprising: at least an array of configurable interconnects including a configurable interconnect, wherein said configurable interconnect selectively realizes an interconnect from an interconnect library; at least an array of configurable logic elements including a configurable logic element, wherein said configurable logic element selectively realizes a logic function from a logic library; and at least an array of configurable computing elements including first and second configurable computing elements, wherein said first configurable computing element comprises a first memory for storing a first look-up table (LUT) for a first math function; and, said second configurable computing element comprises a second memory for storing a second LUT for a second math function; whereby said configurable computing array realizes a complex math function by programming said configurable interconnects, said configurable logic elements and said configurable computing elements, wherein said complex math function is a combination of at least said first and second math functions. ### Claim 12 (depends on 11) The configurable computing array according to claim 11, wherein said configurable computing elements comprises a re-programmable memory, whereby each of said configurable computing elements can be re-configured to realize a different math function by loading the LUT for said different math function into said re-programmable memory. ### Claim 13 (depends on 11) The configurable computing array according to claim 11, wherein at least a first portion of said configurable logic elements and at least a second portion of said configurable computing elements are disposed on a same physical level. ### Claim 14 (depends on 11) The configurable computing array according to claim 11, wherein at least a first portion of said configurable logic elements and at least a second portion of said configurable computing elements are disposed on different physical levels. ### Claim 15 (depends on 14) The configurable computing array according to claim 14, wherein said first and second memories comprise at least a three-dimensional memory (3D-M) array. ### Claim 16 (depends on 15) The configurable computing array according to claim 15, wherein said 3D-M array is a three-dimensional horizontal memory (3D-MH) array or a three-dimensional vertical memory (3D-MV) array. ### Claim 17 (depends on 15) The configurable computing array according to claim 15, wherein said 3D-M array at least partially covers said configurable logic element or said configurable interconnect. ### Claim 18 (depends on 14) The configurable computing array according to claim 14, further comprising a semiconductor substrate with first and second sides, wherein said configurable logic elements are disposed on said first side; said configurable computing elements are disposed on said second side; said configurable logic elements and said configurable computing elements are coupled by a plurality of through-substrate vias through said semiconductor substrate. ### Claim 19 (depends on 14) The configurable computing array according to claim 14, wherein said configurable logic elements are disposed on at least a configurable logic die; said configurable computing elements are disposed on at least a configurable computing die; said configurable logic die and said configurable computing die are located in a same package. ### Claim 20 (depends on 11) The configurable computing array according to claim 11, further comprising at least one multiplier.