# US 10,312,916 B2 · Dynamic decode circuit with delayed precharge > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,312,916 B2 - Document ID: US10312916B2 - Status: Granted - Kind: B2 - Application number: 16/029,607 - Filed: 2018-07-08 - Published: 2018-11-08 - Granted: 2019-06-04 - Earliest claimed: 2016-09-23 - Assignees: International Business Machines Corporation - Applicants: International Business Machines Corporation - Inventors: Paul Alan Bunce; Yuen Hung Chan; John D Davis; Antonio Raffaele Pelella - Web page: https://patentgrep.com/patent/US10312916B2 ## CPC - H03K 19/0963: {using transistors of complementary type (H03K19/0966 takes precedence)} - G11C 8/10: Decoders - G11C 8/18: Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract A dynamic decode circuit for decoding a plurality of input signals comprises precharge circuits that consist of two serially connected transistors, that utilize an evaluate clock and a delayed evaluate clock, that delay the start of a precharge phase for a predetermined period after the end of an evaluation phase. ## Claims ### Claim 1 A dynamic decode circuit connected between a first power source and a second power source, the dynamic decode circuit comprising a decoder connected to a first node and an evaluate clock circuit connected to a second node, wherein the decoder is configured to decode a plurality of inputs, wherein the evaluate clock circuit is configured to present a result of the decode to the second node, wherein the first node of the decoder is conductively connected to a gate of a first transistor of the evaluate clock circuit, wherein the dynamic decode circuit further comprises one or more evaluate transistors, wherein each evaluate transistor is connected to the first power source, wherein the each evaluate transistor is configured to receive an identical evaluation clock signal at a respective base, wherein a third node of the decoder is conductively connected to a first evaluate transistor, wherein the each evaluate transistor is configured to conduct based on the evaluation clock signal being active, wherein the each evaluate transistor is configured not to conduct based on the evaluation clock signal being inactive, and wherein the dynamic decode circuit further comprises one or more precharge circuits, wherein at least one of the one or more precharge circuits is a delay precharge circuit, wherein the delay precharge circuit consists of a respective first precharge transistor serially connected to a respective second precharge transistor, wherein a gate of the first precharge transistor is configured to receive the evaluation clock signal, and a gate of the second precharge transistor is configured to receive a delayed evaluation clock signal, each precharge circuit is conductively connected to the second power source, wherein the each precharge circuit is configured to precharge a respective node based on the evaluation clock signal being inactive, and the precharge circuit configured to not conduct based on the evaluation clock signal being active, wherein the first node is conductively connected to a first delay precharge circuit. ### Claim 2 (depends on 1) The dynamic decode circuit according to claim 1, wherein the evaluation clock circuit is conductively connected to a second delay precharge circuit. ### Claim 3 (depends on 2) The dynamic decode circuit according to claim 2, wherein the evaluation clock circuit consists of the first transistor serially connected to a second transistor, by an interconnecting node, the second transistor being a second evaluate transistor, wherein the evaluation clock circuit is connected to a third delay precharge circuit and the first power source. ### Claim 4 (depends on 1) The dynamic decode circuit according to claim 1, wherein the dynamic decode circuit comprises a conditioning circuit, wherein the conditioning circuit is connected to one or more other conditioning circuits of one or more other dynamic decode circuits, wherein the conditioning circuit is a precharge transistor of a precharge circuit. ### Claim 5 (depends on 4) The dynamic decode circuit according to claim 4, wherein size of the conditioning transistor is determined by a ratio of a predetermined maximum number to a total number of dynamic decode circuits of a configuration, wherein the predetermined maximum number is a maximum number of decoders of the configuration that can conduct in any clock cycle. ### Claim 6 (depends on 5) The dynamic decode circuit according to claim 5, wherein the predetermined maximum number is 1. ### Claim 7 (depends on 1) The dynamic decode circuit according to claim 1, wherein the dynamic decode circuit comprises a conditioning circuit connected, wherein the conditioning circuit is connected to one or more other conditioning circuits of one or more other dynamic decode circuits, wherein the conditioning circuit is an evaluate transistor. ### Claim 8 (depends on 1) The dynamic decode circuit according to claim 1, wherein the each precharge circuit consists of one or more pfet transistors. ### Claim 9 (depends on 1) The dynamic decode circuit according to claim 1, wherein the each evaluate transistor is an nfet transistor. ### Claim 10 (depends on 1) The dynamic decode circuit according to claim 1, wherein the decoder comprises a plurality of decode transistors, wherein the decode transistors are configured to cause the first node to be in a first state based on input signals being in a first input signal state and the evaluation clock signal being active, wherein the decode transistors are configured to cause the first node to be in a second state based on the input signals being in a second input signal state other than the first input signal state and the evaluation clock signal being active. ### Claim 11 (depends on 1) The dynamic decode circuit according to claim 1, wherein the each precharge circuit is a delay precharge circuit, wherein the each delay precharge circuit is configured to precharge a respective node based on both the evaluation clock signal and the delayed evaluation clock signal being inactive, wherein the precharge circuit is configured to not conduct based on the evaluation clock signal being active, and wherein the precharge circuit is configured to not conduct based on any one of the evaluation clock signal and the delayed evaluation clock signal being active. ### Claim 12 A dynamic decode circuit connected between a first power source and a second power source, the dynamic decode circuit comprising a decoder connected to a first node and an evaluate clock circuit connected to a second node, wherein the decoder is configured to decode a plurality of inputs, wherein the evaluate clock circuit is configured to present a result of the decode to the second node, wherein the first node of the decoder is conductively connected to a gate of a first transistor of the evaluate clock circuit, and wherein the dynamic decode circuit further comprises one or more precharge circuits, wherein at least one of the one or more precharge circuits is a delay precharge circuit, wherein the dynamic decode circuit further comprising one or more evaluate transistors, each evaluate transistor connected to the first power source, the each evaluate transistor configured to receive an identical evaluation clock signal at a respective base, wherein a third node, of the decoder is conductively connected to a first evaluate transistor, wherein the each evaluate transistor is configured to conduct based on the evaluation clock signal being active, wherein the each evaluate transistor is configured to not conduct based on the evaluation clock signal being inactive, wherein each delay precharge circuit is configured to start a precharge of a respective node a predetermined delay after an evaluation clock signal going inactive, wherein the each delay precharge circuit is configured to end the precharge of the respective node based on the evaluation clock signal going active, wherein the first node is conductively connected to a first delay precharge circuit. ### Claim 13 (depends on 12) The dynamic decode circuit according to claim 12, wherein the evaluation clock circuit is conductively connected to a second delay precharge circuit. ### Claim 14 (depends on 13) The dynamic decode circuit according to claim 13, wherein the evaluation clock circuit consists of the first transistor serially connected to a second transistor, by an interconnecting node, the second transistor being a second evaluate transistor, wherein the evaluation clock circuit is connected to a third delay precharge circuit and the first power source. ### Claim 15 (depends on 14) The dynamic decode circuit according to claim 14, wherein the dynamic decode circuit comprises a conditioning circuit, wherein the conditioning circuit is connected to one or more other conditioning circuits of one or more other dynamic decode circuits, wherein the conditioning circuit is a precharge transistor of a precharge circuit.