# US 10,312,911 B2 · Programmable analog and digital input/output for power application > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,312,911 B2 - Document ID: US10312911B2 - Status: Granted - Kind: B2 - Application number: 15/984,149 - Filed: 2018-05-18 - Published: 2018-09-20 - Granted: 2019-06-04 - Earliest claimed: 2016-07-21 - Assignees: AnDAPT, Inc. - Applicants: AnDAPT, Inc. - Inventors: John Birkner; Kapil Shankar; Herman Cheung; Patrick J. Crotty; Ranajit Ghoman - Web page: https://patentgrep.com/patent/US10312911B2 ## CPC - H03K 19/017581: {programmable} - H02M 3/1588: {comprising at least one synchronous rectifier element (H02M3/1582, H02M3/1584 take precedence)} - H03K 5/24: the characteristic being amplitude - H03K 17/162: {without feedback from the output circuit to the control circuit} - H03K 19/017509: {Interface arrangements} - H03K 19/177: arranged in matrix form - H03K 19/0016: {by using a control or a clock signal, e.g. in order to apply power supply} - Y02B 70/10: Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) - H02M: APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF (transformers H01F; dynamo-electric converters H02K47/00; controlling transformers, reactors or choke coils, control or regulation of electric motors, generators or dynamo-electric converters H02P) - Y02B: CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS ## Abstract A threshold comparator block integrated in a programmable logic device (PLD) is disclosed. The threshold comparator block includes: one or more signal comparators configured to receive two analog input signals and provide a digital output signal indicating a comparison result of the two analog input signals; an analog output driver configured to interface with an analog fabric of a programmable fabric of the PLD; a digital input/output (I/O) driver configured to interface with a digital fabric of the programmable fabric of the PLD; and I/O pins configured to provide an interface with a signal wrapper to interface analog and digital signals between the analog output driver and the digital I/O driver and the programmable fabric. The threshold comparator block is configured to interface with one or more adaptive blocks integrated in the PLD via the programable fabric and the signal wrapper. ## Claims ### Claim 1 A threshold comparator block integrated in a programmable logic device (PLD) comprising: an interface to a programmable fabric of the PLD via a signal wrapper, wherein the programmable fabric comprises a digital fabric and an analog fabric; and one or more signal comparators configured to receive two analog input signals from the analog fabric of the programmable fabric and provide a digital output signal indicating a comparison result of the two analog input signals to the digital fabric of the programmable fabric, wherein the threshold comparator block is configured to interface with one or more adaptive blocks integrated in the PLD via the programable fabric and the signal wrapper. ### Claim 2 (depends on 1) The threshold comparator block of claim 1, further comprising a digital input/output (I/O) driver configured to provide the digital output signal to the digital fabric of the programmable fabric. ### Claim 3 (depends on 1) The threshold comparator block of claim 1, wherein the digital output signal of the one or more signal comparators indicates a current direction between the two analog input signals. ### Claim 4 (depends on 1) The threshold comparator block of claim 1, further comprising a summation amplifier configured to receive a plurality of analog input signals including a first analog signal and a second analog signal, and a digital gain and provide an analog output signal to the analog fabric of the programmable fabric that corresponds to a difference between the first analog signal and the second analog signal multiplied by the digital gain. ### Claim 5 (depends on 4) The threshold comparator block of claim 4, wherein the plurality of analog input signals further includes a third analog signal, and the summation amplifier provides the analog output signal that is offset by the third analog signal. ### Claim 6 (depends on 4) The threshold comparator block of claim 4, further comprising one or more multiplexers coupled to a plurality of resistors, wherein the one or more multiplexers are configured to receive the digital gain and adjust the digital gain by changing a ratio of the plurality of resistors. ### Claim 7 (depends on 4) The threshold comparator block of claim 4, further comprising an analog output driver that is configured to drive one or more pins of the PLD and provide the analog output signal to the one or more adaptive blocks integrated in the PLD via the one or more pins. ### Claim 8 (depends on 1) The threshold comparator block of claim 1, further comprising one or more current source blocks configured to provide a general-purpose input/output (GPIO) interface. ### Claim 9 (depends on 8) The threshold comparator block of claim 8, wherein I/O signals of the GPIO interface is analog, digital, or a combination of analog and digital signals. ### Claim 10 (depends on 8) The threshold comparator block of claim 8, wherein the GPIO interface is implemented as a universal serial bus (USB) driver. ### Claim 11 (depends on 8) The threshold comparator block of claim 8, wherein the one or more current source blocks are connected to a respective pad of the USB driver and are switched on or off using the corresponding switches for USB signals. ### Claim 12 (depends on 9) The threshold comparator block of claim 9, wherein the USB signals are received via the signal wrapper. ### Claim 13 A programmable logic device (PLD) comprising: a threshold comparator block; a programmable fabric comprising a digital fabric and an analog fabric; and a signal wrapper configured to provide signals between the threshold comparator block and the programmable fabric; and input/output (I/O) pins configured to interface analog and digital signals between the threshold comparator block and the programmable fabric via the signal wrapper, wherein the threshold comparator block comprises: an interface to the programmable fabric of the PLD via the signal wrapper; and one or more signal comparators configured to receive two analog input signals from the analog fabric of the programmable fabric and provide a digital output signal indicating a comparison result of the two analog input signals to the digital fabric of the programmable fabric, wherein the threshold comparator block is configured to interface with one or more adaptive blocks integrated in the PLD via the programable fabric and the signal wrapper. ### Claim 14 (depends on 13) The PLD of claim 13, wherein the threshold comparator block further comprises a digital I/O driver configured to provide the digital output signal to the digital fabric of the programmable fabric. ### Claim 15 (depends on 13) The PLD of claim 13, wherein the threshold comparator block further comprises a summation amplifier configured to receive a plurality of analog input signals including a first analog signal and a second analog signal, and a digital gain and provide an analog output signal to the analog fabric of the programmable fabric that corresponds to a difference between the first analog signal and the second analog signal multiplied by the digital gain. ### Claim 16 (depends on 15) The PLD of claim 15, wherein the plurality of analog input signals further includes a third analog signal, and the summation amplifier provides the analog output signal that is offset by the third analog signal. ### Claim 17 (depends on 15) The PLD of claim 15, wherein the threshold comparator block further comprises an analog output driver that is configured to drive one or more pins of the PLD and provide the analog output signal to the one or more adaptive blocks integrated in the PLD via the one or more pins. ### Claim 18 (depends on 13) The PLD of claim 13, wherein the threshold comparator block further comprises one or more current source blocks configured to provide a general-purpose input/output (GPIO) interface. ### Claim 19 (depends on 18) The PLD of claim 18, wherein I/O signals of the GPIO interface is analog, digital, or a combination of analog and digital signals. ### Claim 20 (depends on 18) The PLD of claim 18, wherein the GPIO interface is implemented as a universal serial bus (USB) driver. ### Claim 21 (depends on 20) The PLD of claim 20, wherein the one or more current source blocks are connected to a respective pad of the USB driver and are switched on or off using the corresponding switches for USB signals. ### Claim 22 (depends on 21) The PLD of claim 21, wherein the USB signals are received via the signal wrapper.