# US 10,312,902 B2 · Low-area, low-power, power-on reset circuit

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- Number: US 10,312,902 B2
- Document ID: US10312902B2
- Status: Granted
- Kind: B2
- Application number: 15/337,587
- Filed: 2016-10-28
- Published: 2018-05-03
- Granted: 2019-06-04
- Earliest claimed: 2016-10-28
- Assignees: Analog Devices Global
- Applicants: Analog Devices Global
- Inventors: Amit Kumar Singh; Sriram Ganesan
- Web page: https://patentgrep.com/patent/US10312902B2

## CPC

- H03K 17/223: {in field-effect transistor switches}
- H03K 2217/0036: Means reducing energy consumption
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)

## Abstract

This application discusses techniques for providing a power-on reset (POR) circuit. The techniques take advantage of the small size of active devices, consume very little current and can use a native NMOS transistor to provide a stable reference over temperature and voltage variations.

## Claims

### Claim 1

A circuit for providing a power-on reset signal, the circuit comprising:
a first native NMOS transistor configured to generate a reference current indicative of a voltage threshold;
a comparator transistor having a control node coupled to the first native NMOS transistor, the comparator transistor configured to compare a sense current with the reference current, wherein the sense current is indicative of a level of a supply voltage of the circuit;
wherein a first node of the comparator transistor is configured to maintain a first state when the reference current is greater than the sense current;
wherein the first node is configured to maintain a second state when the sense current is greater than the reference current; and
a second transistor coupled in series with the first native NMOS transistor and a ground reference, the second transistor having a control node coupled to the supply voltage, the second transistor configured to control variations of the reference current set by the first native NMOS transistor.

### Claim 2 (depends on 1)

The circuit of claim 1, including a current mirror configured to mirror the reference current to the first node of the comparator transistor.

### Claim 3 (depends on 2)

The circuit of claim 2, wherein the current mirror includes a sense transistor and a mirror transistor; and
wherein the control node of the comparator transistor is coupled to a control node of the sense transistor and to a control node of the mirror transistor.

### Claim 4 (depends on 1)

The circuit of claim 1, wherein the second transistor is a a second native NMOS transistor.

### Claim 5 (depends on 4)

The circuit of claim 4, including a third native NMOS transistor coupled in series with the comparator transistor and the ground reference, the third native NMOS transistor having a control node coupled to the supply voltage.

### Claim 6 (depends on 5)

The circuit of claim 5, wherein the second native NMOS transistor includes a plurality of native NMOS transistors arranged in a stack.

### Claim 7 (depends on 5)

The circuit of claim 5, wherein the third native NMOS transistor includes multiple native NMOS transistors arranged in a stack.

### Claim 8 (depends on 5)

The circuit of claim 5, wherein the circuit occupies an area of less than 0.01 mm2.

### Claim 9 (depends on 5)

The circuit of claim 5, wherein the circuit is configured to use 42 nano-amperes (nA) or less on average.

### Claim 10 (depends on 5)

The circuit of claim 5, wherein the threshold voltage associated with the reference current is configured to vary less than 330 millivolts (mV) over a temperature range of −40° C. to 125° C.

### Claim 11

A power-on reset circuit comprising:
a first native NMOS transistor configured to generate a reference current
a current mirror configured to mirror the reference current,
a comparator transistor configured to receive and compare the reference current with a sense current indicative of a supply voltage; and
second and third native NMOS transistors;
wherein a sense transistor of the current mirror is coupled to ground via the first native NMOS transistor and the second native NMOS transistor;
wherein a mirror transistor of the current mirror is coupled to ground via the comparator transistor and the third native NMOS transistor;
wherein a control node of the comparator transistor is coupled to a control node of the sense transistor and to a control node of the mirror transistor; and
wherein a node coupling the mirror transistor to the comparator transistor provides an output of the power-on reset circuit.

### Claim 12 (depends on 11)

The power-on reset circuit of claim 11, the power-on reset circuit occupies an area of less than 0.01 mm2.

### Claim 13 (depends on 11)

The power-on reset circuit of claim 11, including a buffer coupled to a drain of the comparator transistor and configured to provide a second output of the power-on reset circuit.

### Claim 14 (depends on 13)

The power-on reset circuit of claim 13, wherein the buffer includes an inverter.

### Claim 15

A method for providing a power-on reset signal, the method comprising:
generating a reference current indicative of a voltage threshold using a first native NMOS transistor, wherein the generating the reference current includes setting a level of the reference current using a second transistor coupled between a second node of the first native NMOS transistor and the ground, wherein a control node of the second transistor is coupled to the supply voltage;
comparing the reference current to the sense current, the sense current indicative of a level of the supply voltage of a circuit responsive to the power-on reset signal;
setting an output of a comparison circuit to a first state if the reference current is greater than the sense current;
setting the output of the comparison circuit to a second state if the sense current is greater than the reference current.

### Claim 16 (depends on 15)

The method of claim 15, wherein the generating the reference current includes coupling a control node of the first native NMOS transistor to a ground.

### Claim 17 (depends on 15)

The method of claim 15, wherein the comparing the reference current to a sense current includes:
mirroring the reference current to a first node of a comparator transistor using a mirror transistor of a current mirror, the mirror transistor coupled between the comparator transistor and the supply voltage;
generating a control voltage from a node common to a sense transistor of the current mirror and to the first native NMOS transistor;
receiving the control voltage at a control node of the comparator transistor.

### Claim 18 (depends on 17)

The method of claim 17, wherein the comparing the reference current to a sense current includes generating the sense current at the comparator transistor using the control voltage.

### Claim 19 (depends on 15)

The method of claim 15, wherein the second transistor is a second native NMOS transistor.

### Claim 20 (depends on 19)

The method of claim 19, wherein the second native NMOS transistor includes a plurality of native NMOS transistor coupled in a stack configuration.