# US 10,312,895 B2 · Apparatus and method for instant-on quadra-phase signal generator

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- Number: US 10,312,895 B2
- Document ID: US10312895B2
- Status: Granted
- Kind: B2
- Application number: 16/028,253
- Filed: 2018-07-05
- Published: 2018-11-01
- Granted: 2019-06-04
- Earliest claimed: 2016-08-23
- Assignees: Micron Technology, Inc.
- Applicants: Micron Technology, Inc.
- Inventors: Yantao Ma
- Web page: https://patentgrep.com/patent/US10312895B2

## CPC

- H03K 5/15013: {with more than two outputs}
- G11C 7/222: {Clock generating, synchronizing or distributing circuits within memory device}
- G11C 8/10: Decoders
- G11C 11/4076: Timing circuits (for regeneration management G11C11/406)
- H03B 27/00: Generation of oscillations providing a plurality of outputs of the same frequency but differing in phase, other than merely two anti-phase outputs
- H03D 7/165: {at least two frequency changers being located in different paths, e.g. in two paths with carriers in quadrature (combined with amplitude demodulation H03D1/2245, combined with angle demodulation H03D3/007; N-path filters H03H19/002)}
- G11C 7/20: Memory cell initialisation circuits, e.g. when powering up or down, memory clear, latent image memory
- G11C 11/4072: Circuits for initialization, powering up or down, clearing memory or presetting
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H03B: GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS (generators adapted for electrophonic musical instruments G10H; masers or lasers H01S; generation of oscillations in plasma H05H)
- H03D: DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER (masers, lasers H01S; circuits capable of acting both as modulator and demodulator H03C; details applicable to both modulators and frequency-changers H03C; demodulating pulses H03K9/00; transforming types of pulse modulation H03K11/00; coding, decoding or code conversion, in general H03M; repeater stations H04B7/14; demodulators adapted for AC systems of digital information transmission H04L27/00; synchronous demodulators adapted for colour television H04N9/66)

## Abstract

Apparatuses are provided for a quadra-phase clock signal generator. An example apparatus includes a first delay circuit configured to receive a first input clock signal generating a first delayed clock signal. A first phase mixer is provided communicatively coupled to the first delay circuit and configured to receive the first delayed clock signal at a first input and a second input clock signal at a second input. The first phase mixer may then generate a first output clock signal at a first output node responsive, at least in part, to mixing of the first delayed clock signal and the second input clock signal.

## Claims

### Claim 1

An apparatus comprising:
a first delay circuit configured to receive a first input clock signal and generate a first delayed clock signal, the first delay circuit configured to adjust a delay of the first delayed clock signal based, at least in part, on a period of the first input clock signal; and
a first phase mixer coupled to the first delay circuit and configured to generate a first output clock signal responsive, at least in part, to mixing of the first delayed clock signal and a second input clock signal.

### Claim 2 (depends on 1)

The apparatus of claim 1, wherein the first phase mixer comprises a first input and a second input.

### Claim 3 (depends on 2)

The apparatus of claim 2, wherein the first delayed clock signal is received at the first input of the first phase mixer and the second input clock signal is received at the second input of the first phase mixer.

### Claim 4 (depends on 1)

The apparatus of claim 1, further comprising a second delay circuit configured to receive the second input clock signal and generate a second delayed clock signal.

### Claim 5 (depends on 4)

The apparatus of claim 4, further comprising a second phase mixer coupled to the second delay circuit and configured to receive the second delayed clock signal at a third input and the first input clock signal at a fourth input.

### Claim 6 (depends on 5)

The apparatus of claim 5, wherein the second phase mixer is configured to generate a second output clock signal responsive, at least in part, to mixing the second delayed clock signal and the first input clock signal.

### Claim 7 (depends on 6)

The apparatus of claim 6, wherein the first delay circuit is configured to generate a third delayed clock signal, wherein the third delayed clock signal has less delay than the first delayed clock signal.

### Claim 8 (depends on 7)

The apparatus of claim 7, wherein the second delay circuit is further configured to generate a fourth delayed clock signal, wherein the fourth delayed clock signal has less delay than the second delayed clock signal.

### Claim 9 (depends on 8)

The apparatus of claim 8, further comprising:
a first buffer configured to generate a third output clock signal based on the third delayed clock signal; and
a second buffer configured to generate a fourth output clock signal based on the fourth delayed clock signal.

### Claim 10 (depends on 9)

The apparatus of claim 9, wherein each of the first and second delay buffers is configured to have a propagation delay that matches a propagation delay of each of the first phase mixer and the second phase mixer.

### Claim 11

A method comprising:
generating a first delayed clock signal in response to receiving a first input clock signal;
adjusting a delay of the first delayed clock signal based, at least in part, on a period of the first input clock signal; and
generating a first output clock signal responsive, at least in part, to mixing the first delayed clock signal and a second input clock signal.

### Claim 12 (depends on 11)

The method of claim 11, further comprising receiving the first delayed clock signal at a first input of a first phase mixer.

### Claim 13 (depends on 12)

The method of claim 12, further comprising receiving the second input clock signal at a second input of the first phase mixer.

### Claim 14 (depends on 13)

The method of claim 13, further comprising generating a second delayed clock signal, via a second delay circuit, wherein the second delayed clock signal is received at a second phase mixer.

### Claim 15 (depends on 14)

The method of claim 14, further comprising generating a second output clock signal responsive; at least in part, to mixing the second delayed clock signal and the first input clock signal.

### Claim 16 (depends on 15)

The method of claim 15, further comprising generating a third delayed clock signal, via a first delay circuit, wherein the third delayed clock signal has less delay than the first delayed clock signal.

### Claim 17 (depends on 16)

The method of claim 16, further comprising generating a fourth delayed clock signal, via the second delay circuit, wherein the fourth delayed clock signal has less delay than the second delayed clock signal.

### Claim 18 (depends on 17)

The method of claim 17, further comprising:
generating, via a first buffer, a third output clock signal based on the third delayed clock signal; and
generating, via a second buffer, a fourth output clock signal based on the fourth delayed clock signal.

### Claim 19 (depends on 18)

The method of claim 18, further comprising exhibiting a propagation delay at both the first and second buffers that matches a propagation delay of the first and second phase mixers.

### Claim 20 (depends on 18)

The method of claim 18, wherein generating the first output clock signal includes generating a 90-degree phase output clock signal, wherein generating the second output clock signal includes generating a 270-degree phase output clock signal, wherein generating the third output clock signal includes generating a 0-degree phase output clock signal, and wherein generating the fourth output clock signal includes generating a 180-degree phase output clock signal.