# US 10,312,894 B2 · Apparatuses and methods for providing a signal with a differential phase mixer > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,312,894 B2 - Document ID: US10312894B2 - Status: Granted - Kind: B2 - Application number: 16/144,772 - Filed: 2018-09-27 - Published: 2019-01-31 - Granted: 2019-06-04 - Earliest claimed: 2015-11-25 - Assignees: Micron Technology, Inc. - Applicants: Micron Technology, Inc. - Inventors: Yantao Ma - Web page: https://patentgrep.com/patent/US10312894B2 ## CPC - H03K 5/135: by the use of time reference signals, e.g. clock signals - H03K 2005/00052: {by mixing the outputs of fixed delayed signals with each other or with the input signal} - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) ## Abstract According to one embodiment, an apparatus is described. The apparatus comprises a first phase mixer circuit configured to receive a first signal and a second signal and provide a first intermediate signal having a phase between a phase of the first signal and a phase of the clock signal. The apparatus further comprises a second phase mixer circuit configured to receive a complement of the first signal and a complement of the second signal and provide a second intermediate signal having a phase between a phase of the complement of the first signal and a phase of the complement of the second signal, wherein the second intermediate signal is combined with the first intermediate signal at a node to provide an output signal. ## Claims ### Claim 1 An apparatus comprising: a phase interpolation circuit including first and second phase mixer circuits including corresponding first inverters, corresponding second inverters, corresponding third inverters, and corresponding fourth inverters, the corresponding first inverters of the first and second phase mixer circuits configured to receive, respectively, a first input signal and a complimentary first input signal, each of the corresponding first inverters of the first and second phase mixer circuits configured to be controlled by a first control signal received, via the corresponding second inverter, at a non-inverting control input of the corresponding first inverter, each of the corresponding first inverters of the first and second phase mixer circuits further configured to be controlled by the first control signal received at an inverting control input of the corresponding first inverter, the corresponding third inverters of the first and second phase mixer circuits configured to receive, respectively, a second input signal and a complimentary second input signal, each of the corresponding third inverters of the first and second phase mixer circuits configured to be controlled by a second control signal received, via the corresponding fourth inverter, at an inverting control input of the corresponding third inverter, each of the corresponding third inverters of the first and second phase mixer circuits further configured to be controlled by the second control signal received at a non-inverting control input of the corresponding third inverter, the phase interpolation circuit configured to provide an output signal based on corresponding outputs of the first and second phase mixer circuits. ### Claim 2 (depends on 1) The apparatus of claim 1, wherein the corresponding first inverters of the first and second phase mixer circuits are configured to provide corresponding first internal output signals to corresponding output nodes of the first and second phase mixer circuits. ### Claim 3 (depends on 2) The apparatus of claim 2, wherein the corresponding third inverters of the first and second phase mixer circuits are configured to provide corresponding second internal output signals to the corresponding output nodes of the first and second phase mixer circuits. ### Claim 4 (depends on 3) The apparatus of claim 3, wherein the corresponding output nodes of the first and second phase mixer circuits are configured to output, respectively, first and second intermediate signals from the corresponding outputs of the first and second phase mixer circuits. ### Claim 5 (depends on 4) The apparatus of claim 4, wherein the first intermediate signal experiences a first duty cycle variation and the second intermediate signal experiences a second duty cycle variation that is complementary to the first duty cycle variation. ### Claim 6 (depends on 4) The apparatus of claim 4, further comprising: a first output inverter coupled between the corresponding output node of the second phase mixer circuit and a shared output node; and a second output inverter coupled between the corresponding output node of the second phase mixer circuit and the shared output node. ### Claim 7 (depends on 6) The apparatus of claim 6, wherein the corresponding output node of the second phase mixer circuit is coupled to an input of the first output inverter, and the shared output node is coupled to an output of the first output inverter, and wherein the corresponding output node of the second phase mixer circuit is coupled to an output of the second output inverter, and the shared output node is coupled to an input of the second output inverter. ### Claim 8 (depends on 6) The apparatus of claim 6, wherein the first and second output inverters are coupled in a latch configuration. ### Claim 9 An apparatus comprising: a phase interpolation circuit including first and second phase mixer circuits and configured to provide an output signal based on corresponding outputs of the first and second phase mixer circuits, the first and second phase mixer circuits including corresponding first inverters, corresponding second inverters, corresponding third inverters, and corresponding fourth inverters, the corresponding first inverters of the first and second phase mixer circuits configured to receive, respectively, a first input signal and a complimentary first input signal, each of the corresponding first inverters of the first and second phase mixer circuits configured to be controlled by a first control signal received, via the corresponding second inverter, at a non-inverting control input of the corresponding first inverter, the corresponding first inverters of the first and second phase mixer circuits configured to provide corresponding first internal output signals to corresponding output nodes of the first and second phase mixer circuits, the corresponding third inverters of the first and second phase mixer circuits configured to receive, respectively, a second input signal and a complimentary second input signal, each of the corresponding third inverters of the first and second phase mixer circuits configured to be controlled by a second control signal received, via the corresponding fourth inverter, at an inverting control input of the corresponding third inverter, the corresponding third inverters of the first and second phase mixer circuits configured to provide corresponding second internal output signals to the corresponding output nodes of the first and second phase mixer circuits, the corresponding output nodes of the first and second phase mixer circuits configured to output, respectively, first and second intermediate signals from the corresponding outputs of the first and second phase mixer circuits. ### Claim 10 (depends on 9) The apparatus of claim 9, wherein the first intermediate signal experiences a first duty cycle variation and the second intermediate signal experiences a second duty cycle variation that is complementary to the first duty cycle variation. ### Claim 11 (depends on 9) The apparatus of claim 9, further comprising: a first output inverter coupled between the corresponding output node of the second phase mixer circuit and a shared output node; and a second output inverter coupled between the corresponding output node of the second phase mixer circuit and the shared output node. ### Claim 12 (depends on 11) The apparatus of claim 11, wherein the corresponding output node of the second phase mixer circuit is coupled to an input of the first output inverter, and the shared output node is coupled to an output of the first output inverter, and wherein the corresponding output node of the second phase mixer circuit is coupled to an output of the second output inverter, and the shared output node is coupled to an input of the second output inverter. ### Claim 13 (depends on 12) The apparatus of claim 12, wherein the first and second output inverters are coupled in a latch configuration. ### Claim 14 An apparatus comprising: a phase interpolation circuit including first and second phase mixer circuits configured to provide an output signal based on corresponding outputs of the first and second phase mixer circuits, the first and second phase mixer circuits including corresponding first inverters, corresponding second inverters, corresponding third inverters, and corresponding fourth inverters, the corresponding first inverters of the first and second phase mixer circuits configured to receive, respectively, a first input signal and a complimentary first input signal, each of the corresponding first inverters of the first and second phase mixer circuits configured to be controlled by a first control signal received, via the corresponding second inverter, at a non-inverting control input of the corresponding first inverter, the corresponding third inverters of the first and second phase mixer circuits configured to receive, respectively, a second input signal and a complimentary second input signal, each of the corresponding third inverters of the first and second phase mixer circuits configured to be controlled by a second control signal received, via the corresponding fourth inverter, at an inverting control input of the corresponding third inverter, the first and second phase mixer circuits including corresponding output nodes configured to output, respectively, first and second intermediate signals from the corresponding outputs of the first and second phase mixer circuits, the first intermediate signal output from the corresponding output node of the first phase mixer circuit based on the corresponding first and second input signals received by the first phase mixer circuit, the second intermediate signal output from the corresponding output node of the second phase mixer circuit based on the corresponding first and second input signals received by the second phase mixer circuit. ### Claim 15 (depends on 14) The apparatus of claim 14, wherein the first intermediate signal output from the first phase mixer circuit is provided to a shared output node, and wherein the second intermediate signal output from the second phase mixer circuit is provided to the shared output node. ### Claim 16 (depends on 15) The apparatus of claim 15, further comprising: a first output inverter coupled between the corresponding output node of the second phase mixer circuit and the shared output node, wherein the second intermediate signal output from the second phase mixer circuit is provided, via the first output inverter, to the shared output node. ### Claim 17 (depends on 16) The apparatus of claim 16, further comprising: a second output inverter coupled between the corresponding output node of the second phase mixer circuit and the shared output node. ### Claim 18 (depends on 17) The apparatus of claim 17, wherein the first and second output inverters are coupled in a latch configuration. ### Claim 19 (depends on 18) The apparatus of claim 18, wherein the corresponding output node of the second phase mixer circuit is coupled to an input of the first output inverter, and the shared output node is coupled to an output of the first output inverter. ### Claim 20 (depends on 19) The apparatus of claim 19, wherein the corresponding output node of the second phase mixer circuit is coupled to an output of the second output inverter, and the shared output node is coupled to an input of the second output inverter.