# US 10,312,891 B1 · Variation tracking and compensating for small capacitor > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,312,891 B1 - Document ID: US10312891B1 - Status: Granted - Kind: B1 - Application number: 16/142,476 - Filed: 2018-09-26 - Granted: 2019-06-04 - Earliest claimed: 2018-09-26 - Assignees: QUALCOMM Incorporated - Applicants: QUALCOMM Incorporated - Inventors: Chao Song; Zhengzheng Wu; Haitao Cheng; Ye Lu - Web page: https://patentgrep.com/patent/US10312891B1 ## CPC - H03K 5/00: Manipulating of pulses not covered by one of the other main groups of this subclass (circuits with regenerative action H03K3/00, H03K4/00; by the use of non-linear magnetic or dielectric devices H03K3/45) - H10D 1/714: {having horizontal extensions} - H10D 84/811: {Combinations of field-effect devices and one or more diodes, capacitors or resistors} - H10W 20/496: {Capacitor integral with wiring layers} - H10W 20/498: {Resistive arrangements or effects of, or between, wiring layers} - H03K 19/20: characterised by logic function, e.g. AND, OR, NOR, NOT circuits (H03K19/003 - H03K19/01 take precedence) - H03K 2005/00019: {Variable delay} - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract In certain aspects, an integrated circuit comprises a signal path having a path delay from an input to an output, wherein the signal path comprises a path capacitor having a path capacitance. The integrated circuit also comprises a variation tracking circuit coupled to the signal path, wherein the variation tracking circuit comprises a tracking resistor have a tracking resistance, and wherein a product of the tracking resistance and the path capacitance is substantially constant over process variation. ## Claims ### Claim 1 An integrated circuit, comprising: a signal path having a path delay from an input to an output, wherein the signal path comprises a path capacitor having a path capacitance; and a variation tracking circuit coupled to the signal path, wherein the variation tracking circuit comprises a tracking resistor having a tracking resistance, and wherein a product of the tracking resistance and the path capacitance is substantially constant over process variation. ### Claim 2 (depends on 1) The integrated circuit of claim 1, wherein the path delay is substantially constant over process variation. ### Claim 3 (depends on 1) The integrated circuit of claim 1, wherein the path capacitor and the tracking resistor are next to each other. ### Claim 4 (depends on 1) The integrated circuit of claim 1, wherein the path capacitor comprises at least two interdigitated fingers in a same metal layer having a finger width and a finger spacing, and wherein the tracking resistor comprises a metal line having the finger width and the finger spacing on the same metal layer. ### Claim 5 (depends on 1) The integrated circuit of claim 1, wherein the path capacitor comprises a plate capacitor having a first plate in a first metal layer, a second plate in a second metal layer, and a dielectric layer between the first metal layer and the second metal layer, and wherein the tracking resistor comprises a plurality of vias in the dielectric layer connecting serially through a plurality of metal pieces in the first metal layer and the second metal layer in an alternating order. ### Claim 6 (depends on 1) The integrated circuit of claim 1, wherein the signal path comprises one or more logic gates, and wherein the path capacitor is configured to load at least one of the one or more logic gates. ### Claim 7 (depends on 1) The integrated circuit of claim 1 further comprising a voltage regulator, wherein the variation tracking circuit couples to the signal path through the voltage regulator. ### Claim 8 (depends on 7) The integrated circuit of claim 7, wherein the voltage regulator is configured to provide a supply voltage to the signal path, and wherein the supply voltage is configured to vary in response to a coupling signal from the variation tracking circuit. ### Claim 9 (depends on 8) The integrated circuit of claim 8, wherein the variation tracking circuit is configured to generate a reference current or a reference voltage that tracks the tracking resistance. ### Claim 10 (depends on 9) The integrated circuit of claim 9, wherein the reference current or the reference voltage is configured to couple to the voltage regulator. ### Claim 11 (depends on 9) The integrated circuit of claim 9, wherein the supply voltage of the signal path is configured to vary in response to the reference current or the reference voltage. ### Claim 12 (depends on 9) The integrated circuit of claim 9, wherein the variation tracking circuit comprises a first transistor having a first gate, a first drain coupled to a current mirror, and a first source coupled to a first terminal of the tracking resistor, wherein a second terminal of the tracking resistor coupled a common node; a second transistor having a second gate coupled to the first gate, a second drain coupled to the second gate, and a second source coupled to the common node; and a third transistor having a third gate coupled to the second gate, a third source coupled to the current mirror, and a third drain coupled to the second gate. ### Claim 13 (depends on 12) The integrated circuit of claim 12, wherein the first transistor and the second transistor are of a first type and the third transistor is of a second type. ### Claim 14 (depends on 13) The integrated circuit of claim 13, wherein the first type is NMOS and the second type is PMOS, and wherein the common node is a ground. ### Claim 15 (depends on 14) The integrated circuit of claim 14, wherein the third source couples to the signal path. ### Claim 16 (depends on 14) The integrated circuit of claim 14, wherein the current mirror couples to the signal path. ### Claim 17 A method, comprising: delaying a signal from an input to an output through one or more logic gates having a path delay, wherein at least one of the one or more logic gates is loaded with a path capacitor having a path capacitance; and coupling a variation tracking circuit to the one or more logic gates, wherein the variation tracking circuit comprises a tracking resistor having a tracking resistance, and wherein a product of the tracking resistance and the path capacitance is substantially constant over process variation, and wherein the path delay is substantially constant over process variation. ### Claim 18 (depends on 17) The method of claim 17, wherein the path capacitor and the tracking resistor are next to each other. ### Claim 19 (depends on 17) The method of claim 17, wherein the path capacitor comprises at least two interdigitated fingers in a same metal layer having a finger width and a finger spacing, and wherein the tracking resistor comprises a metal line on the same metal layer having the finger width and the finger spacing. ### Claim 20 (depends on 17) The method of claim 17, wherein the path capacitor comprises a plate capacitor having a first plate in a first metal layer, a second plate in a second metal layer, and a dielectric layer between the first metal layer and the second metal layer, and wherein the tracking resistor comprises a plurality of vias in the dielectric layer connecting serially through a plurality of metal pieces in the first metal layer and the second metal layer in an alternating order. ### Claim 21 (depends on 17) The method of claim 17 further comprising varying a supply voltage of the one or more logic gates in response to a coupling signal from the variation tracking circuit. ### Claim 22 (depends on 21) The method of claim 21, wherein the variation tracking circuit is configured to generate a reference current or a reference voltage that tracks the tracking resistance. ### Claim 23 (depends on 22) The method of claim 22, wherein the supply voltage of the one or more logic gates is varied in response to the reference current or the reference voltage. ### Claim 24 (depends on 17) The method of claim 17, wherein the variation tracking circuit comprises a first transistor having a first gate, a first drain coupled to a current mirror, and a first source coupled to a first terminal of the tracking resistor, wherein a second terminal of the tracking resistor coupled to a common node; a second transistor having a second gate coupled to the first gate, a second drain coupled to the second gate, and a second source coupled the common node; and a third transistor having a third gate coupled to the second gate, a third source coupled to the current mirror, and a third drain coupled to the second gate. ### Claim 25 (depends on 24) The method of claim 24, wherein the third source couples to the one or more logic gates.