# US 10,312,888 B2 · Systems and methods for a robust double node upset tolerant latch

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- Number: US 10,312,888 B2
- Document ID: US10312888B2
- Status: Granted
- Kind: B2
- Application number: 16/110,137
- Filed: 2018-08-23
- Published: 2018-12-20
- Granted: 2019-06-04
- Earliest claimed: 2016-09-15
- Assignees: Board of Trustees of Southern Illinois University on Behalf of Southern Illinois University Carbondale
- Applicants: Adam Watkins; Spyros Tragoudas
- Inventors: Adam Watkins; Spyros Tragoudas
- Web page: https://patentgrep.com/patent/US10312888B2

## CPC

- H03K 3/0375: {provided with means for increasing reliability; for protection; for ensuring a predetermined initial state when the supply voltage has been applied; for storing the actual state when the supply voltage fails (digital storage cells each combining volatile and non-volatile storage properties G11C14/00)}
- H03K 19/08: using semiconductor devices (H03K19/173 takes precedence; wherein the semiconductor devices are only diode rectifiers H03K19/12)
- H03K 19/20: characterised by logic function, e.g. AND, OR, NOR, NOT circuits (H03K19/003 - H03K19/01 take precedence)
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)

## Abstract

Various embodiments of a robust double node upset tolerant latch in which all internal and external nodes are capable of recovering the previous value after a single event upset are disclosed.

## Claims

### Claim 1

A double node upset (DNU) tolerant latch circuit comprising:
a first storage circuit (C1) and a second storage circuit (C2), each comprising three inputs and an output;
a third storage circuit (C3) and a fourth storage circuit (C4), each comprising two inputs and an output;
wherein the output of the first storage circuit (C1) is electrically connected to an input of the second storage circuit (C2); the output of the second storage circuit (C2) is electrically connected to the fourth storage circuit (C4); the output of the third storage circuit (C3) is electrically connected to an input of the second storage circuit (C2); and the output of the fourth storage circuit (C4) is electrically connected to an input of the first storage circuit (C1) and an input of the third storage circuit (C3).

### Claim 2 (depends on 1)

The DNU tolerant latch circuit of claim 1, further comprising:
a voting circuit, the voting circuit comprising:
a first voting element circuit (C5) and a second voting element circuit (C6), each comprising two inputs and an output; and
a third voting element circuit (C7) comprising three inputs and an output, wherein the output of the third voting element circuit (C7) is the output of the DNU tolerant latch circuit.

### Claim 3 (depends on 2)

The DNU tolerant latch circuit of claim 2, wherein:
the output of the first voting element circuit (C5) is electrically connected to an NMOS transistor of the second storage circuit (C2), an input of the third storage circuit (C3), and a PMOS of the third voting element circuit (C7).

### Claim 4 (depends on 3)

The DNU tolerant latch circuit of claim 3, wherein:
the output of the second voting element circuit (C6) is electrically connected to an input of the first storage circuit (C1), a PMOS transistor of the second storage circuit (C2), and an NMOS transistor of the third voting element circuit (C7).

### Claim 5 (depends on 4)

The DNU tolerant latch circuit of claim 4, wherein:
the output of the third voting element circuit (C7) is electrically connected to an input of the fourth storage circuit (C4), a PMOS transistor of the first voting element circuit (C5), and an NMOS transistor of the second voting element circuit (C6).

### Claim 6 (depends on 2)

The DNU tolerant latch circuit of claim 2, wherein:
the output of the first storage circuit (C1) is further electrically connected to an input of the first voting element circuit (C5) and an input of the third voting element circuit (C7).

### Claim 7 (depends on 6)

The DNU tolerant latch circuit of claim 6, wherein the output of the second storage circuit (C2) is further electrically connected to an NMOS transistor of the first voting element circuit (C5), and a PMOS transistor of the second voting element circuit (C6).

### Claim 8 (depends on 7)

The DNU tolerant latch circuit of claim 7, wherein the output of the third storage circuit (C3) is further electrically connected to an input of the second voting element circuit (C6), and an input of the third voting element circuit (C7).

### Claim 9 (depends on 2)

The DNU tolerant latch circuit of claim 2, wherein:
the first voting element circuit (C5) and the second voting element circuit (C6) each comprise a two-input C-element circuit; and
the third voting element circuit (C7) comprises a three-input C-element circuit.

### Claim 10 (depends on 2)

The DNU tolerant latch circuit of claim 2, further comprising:
a first inverter coupled between the output of the first storage circuit (C1) and an input of the third voting element circuit (C7); and
a second inverter coupled between the output of the third storage circuit (C3) and inputs of the second storage circuit (C2) and the third voting element circuit (C7).

### Claim 11 (depends on 1)

The DNU tolerant latch circuit of claim 1, wherein:
the first storage circuit (C1) and the second storage circuit (C2) each comprise a three-input C-element circuit; and
the third storage circuit (C3) and the fourth storage circuit (C4) each comprise a two-input C-element circuit.

### Claim 12 (depends on 1)

The DNU tolerant latch circuit of claim 1, wherein an input of the first storage circuit (C1) is electrically connected to a clock signal.

### Claim 13

A method for preventing double node upsets (DNUs) in a latch circuit, the method comprising:
electrically interconnecting:
a first storage circuit (C1) and a second storage circuit (C2), each comprising three inputs and an output; and
a third storage circuit (C3) and a fourth storage circuit (C4), each comprising two inputs and an output;
wherein the output of the first storage circuit (C1) is electrically connected to an input of the second storage circuit (C2); the output of the second storage circuit (C2) is electrically connected to the fourth storage circuit (C4); the output of the third storage circuit (C3) is electrically connected to an input of the second storage circuit (C2); and the output of the fourth storage circuit (C4) is electrically connected to an input of the first storage circuit (C1) and an input of the third storage circuit (C3).

### Claim 14 (depends on 13)

The method of claim 13, further comprising electrically interconnecting a voting circuit, wherein the voting circuit comprises:
a first voting element circuit (C5) and a second voting element circuit (C6), each comprising two inputs and an output; and
a third voting element circuit (C7) comprising three inputs and an output, wherein the output of the third voting element circuit (C7) is the output of the latch circuit.

### Claim 15 (depends on 14)

The method of claim 14, wherein:
the output of the first voting element circuit (C5) is electrically connected to an NMOS transistor of the second storage circuit (C2), an input of the third storage circuit (C3), and a PMOS of the third voting element circuit (C7).

### Claim 16 (depends on 15)

The method of claim 15, wherein:
the output of the second voting element circuit (C6) is electrically connected to an input of the first storage circuit (C1), a PMOS transistor of the second storage circuit (C2), and an NMOS transistor of the third voting element circuit (C7).

### Claim 17 (depends on 16)

The method of claim 16, wherein:
the output of the third voting element circuit (C7) is electrically connected to an input of the fourth storage circuit (C4), a PMOS transistor of the first voting element circuit (C5), and an NMOS transistor of the second voting element circuit (C6).

### Claim 18 (depends on 14)

The method of claim 14, wherein:
the output of the first storage circuit (C1) is further electrically connected to an input of the first voting element circuit (C5) and an input of the third voting element circuit (C7);
the output of the second storage circuit (C2) is further electrically connected to an NMOS transistor of the first voting element circuit (C5), and a PMOS transistor of the second voting element circuit (C6); and
the output of the third storage circuit (C3) is further electrically connected to an input of the second voting element circuit (C6), and an input of the third voting element circuit (C7).

### Claim 19 (depends on 14)

The method of claim 14, wherein:
the first storage circuit (C1) and the second storage circuit (C2) each comprise a three-input C-element circuit;
the third storage circuit (C3) and the fourth storage circuit (C4) each comprise a two-input C-element circuit;
the first voting element circuit (C5) and the second voting element circuit (C6) each comprise a two-input C-element circuit; and
the third voting element circuit (C7) comprises a three-input C-element circuit.

### Claim 20 (depends on 14)

The method of claim 14, further comprising:
electrically interconnecting:
a first inverter between the output of the first storage circuit (C1) and an input of the third voting element circuit (C7); and
a second inverter between the output of the third storage circuit (C3) and inputs of the second storage circuit (C2) and the third voting element circuit (C7).