# US 10,312,864 B2 · Power amplifier having selective signal paths > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,312,864 B2 - Document ID: US10312864B2 - Status: Granted - Kind: B2 - Application number: 15/458,918 - Filed: 2017-03-14 - Published: 2017-10-19 - Granted: 2019-06-04 - Earliest claimed: 2014-06-30 - Assignees: Skyworks Solutions, Inc. - Applicants: Skyworks Solutions, Inc. - Inventors: Christophe M. Joly; Xiaodong Xu; Eric Joseph Lai - Web page: https://patentgrep.com/patent/US10312864B2 ## CPC - H03F 1/0222: {by using a signal derived from the input signal} - H03F 1/0277: {Selecting one or more amplifiers from a plurality of amplifiers} - H03F 1/56: Modifications of input or output impedances, not otherwise provided for - H03F 3/19: with semiconductor devices only - H03F 3/195: in integrated circuits - H03F 3/245: {with semiconductor devices only} - H03F 3/60: Amplifiers in which coupling networks have distributed constants, e.g. with waveguide resonators (H03F3/54 takes precedence) - H03F 3/68: Combinations of amplifiers, e.g. multi-channel amplifiers for stereophonics {(power amplifiers using a combination of several semiconductor amplifiers H03F3/211; combinations of amplifiers using coupling networks with distributed constants H03F3/602)} - H03F 3/72: Gated amplifiers, i.e. amplifiers which are rendered operative or inoperative by means of a control signal - H04B 1/04: Circuits - H04B 1/44: Transmit/receive switching - H03F 2200/111: the amplifier being a dual or triple band amplifier, e.g. 900 and 1800 MHz, e.g. switched or not switched, simultaneously or not - H03F 2200/204: A hybrid coupler being used at the output of an amplifier circuit - H03F 2200/222: A circuit being added at the input of an amplifier to adapt the input impedance of the amplifier - H03F 2200/387: A circuit being added at the output of an amplifier to adapt the output impedance of the amplifier - H03F 2200/411: the output amplifying stage of an amplifier comprising two power stages - H03F 2200/429: Two or more amplifiers or one amplifier with filters for different frequency bands are coupled in parallel at the input or output - H03F 2200/451: the amplifier being a radio frequency amplifier - H03F 2203/7206: the gated amplifier being switched on or off by a switch in the bias circuit of the amplifier controlling a bias voltage in the amplifier - H03F 2203/7209: the gated amplifier being switched from a first band to a second band - H03F 2203/7236: the gated amplifier being switched on or off by putting into parallel or not, by choosing between amplifiers by (a ) switch(es) - H04B 2001/0408: {with power amplifiers} - H03F: AMPLIFIERS - H04B: TRANSMISSION ## Abstract Power amplifier having selective signal paths. In some embodiments, a power amplifier circuit can include a plurality of signal paths sharing a common amplification stage configured to partially amplify a signal. Each signal path can further include a dedicated amplification stage coupled to the common amplification stage and configured to be capable of further amplifying the partially amplified signal. The power amplifier circuit can further include a bias selector having a switch configured to provide a bias signal to a selected dedicated amplification stage among the plurality of signal paths to thereby allow the selected dedicated amplification stage to further amplify the partially amplified signal. ## Claims ### Claim 1 A power amplifier circuit comprising: a common amplification stage configured to partially amplify a signal; a plurality of dedicated amplification stages, each coupled to the common amplification stage and configured to be capable of further amplifying the partially amplified signal, each dedicated amplification stage including an output node; and a bias selector configured to selectively provide a bias signal to a selected one of the plurality of dedicated amplification stages to thereby allow the selected dedicated amplification stage to further amplify the partially amplified signal and provide the further amplified signal at the respective output node. ### Claim 2 (depends on 1) The power amplifier circuit of claim 1 wherein the bias selector is configured such that the bias signal is provided to an input node of the selected dedicated amplification stage. ### Claim 3 (depends on 1) The power amplifier circuit of claim 1 wherein the bias selector includes a switch having a pole and a number of throws at least as many as the number of dedicated amplification stages. ### Claim 4 (depends on 3) The power amplifier circuit of claim 3 wherein the switch is configured to receive the bias signal through the pole and route the bias signal to the selected dedicated amplifier stage through a corresponding throw. ### Claim 5 (depends on 1) The power amplifier circuit of claim 1 wherein the common amplifier stage is a first amplifier stage in a corresponding signal path. ### Claim 6 (depends on 5) The power amplifier circuit of claim 5 wherein the dedicated amplifier stage is a second amplifier stage in the corresponding signal path. ### Claim 7 (depends on 1) The power amplifier circuit of claim 1 further comprising a harmonic trap circuit for each of at least one of the plurality of dedicated amplification stages. ### Claim 8 (depends on 1) The power amplifier circuit of claim 1 further comprising a matching circuit for each of at least one of the plurality of dedicated amplification stages. ### Claim 9 (depends on 1) The power amplifier circuit of claim 1 further comprising a DC-block capacitor for each of at least one of the plurality of dedicated amplification stages. ### Claim 10 (depends on 1) The power amplifier circuit of claim 1 further comprising a power coupling portion for each of at least one of the plurality of dedicated amplification stages. ### Claim 11 (depends on 10) The power amplifier circuit of claim 10 wherein at least two of the power coupling portions are connected by a power coupling circuit. ### Claim 12 A semiconductor die comprising: a semiconductor substrate; and a power amplifier circuit implemented on the semiconductor die and including a common amplification stage configured to partially amplify a signal, and a plurality of dedicated amplification stages, each coupled to the common amplification stage and configured to be capable of further amplifying the partially amplified signal, each dedicated amplification stage including an output node, the power amplifier circuit further including a bias selector configured to selectively provide a bias signal to a selected one of the plurality of dedicated amplification stages to thereby allow the selected dedicated amplification stage to further amplify the partially amplified signal and provide the further amplified signal at the respective output node. ### Claim 13 (depends on 12) The semiconductor die of claim 12 wherein the semiconductor substrate includes a gallium arsenide substrate. ### Claim 14 (depends on 12) The semiconductor die of claim 12 wherein each of the common amplification stage and the dedicated amplification stages includes a bipolar-junction transistor configured to amplify a signal. ### Claim 15 (depends on 14) The semiconductor die of claim 14 wherein the bipolar-junction transistor includes a heterojunction bipolar transistor. ### Claim 16 A wireless device comprising: a transceiver configured to generate a signal; a power amplifier circuit in communication with the transceiver and including a common amplification stage configured to partially amplify a signal, and a plurality of dedicated amplification stages, each coupled to the common amplification stage and configured to be capable of further amplifying the partially amplified signal, each dedicated amplification stage including an output node, the power amplifier circuit further including a bias selector configured to selectively provide a bias signal to a selected one of the plurality of dedicated amplification stages to thereby allow the selected dedicated amplification stage to further amplify the partially amplified signal and provide the further amplified signal at the respective output node; and an antenna capable of being in communication with the output node of the selected dedicated amplification stage to thereby support transmission of the further amplified signal. ### Claim 17 (depends on 16) The wireless device of claim 16 further comprising a filter implemented between each dedicated amplification stage and the antenna. ### Claim 18 (depends on 17) The wireless device of claim 17 further comprising an antenna switch implemented between the filters associated with the plurality of dedicated amplification stages and the antenna. ### Claim 19 (depends on 18) The wireless device of claim 18 wherein the wireless device is configured to be capable of operating in a time-division duplexing mode. ### Claim 20 (depends on 19) The wireless device of claim 19 wherein the antenna switch is configured to support the time-division duplexing mode of operation.