# US 10,312,803 B1 · Electronic device with a charging mechanism

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- Number: US 10,312,803 B1
- Document ID: US10312803B1
- Status: Granted
- Kind: B1
- Application number: 15/849,137
- Filed: 2017-12-20
- Published: 2019-06-20
- Granted: 2019-06-04
- Earliest claimed: 2017-12-20
- Assignees: Micron Technology, Inc.
- Applicants: Micron Technology, Inc.
- Inventors: Michele Piccardi
- Web page: https://patentgrep.com/patent/US10312803B1

## CPC

- H02M 3/07: using capacitors charged and discharged alternately by semiconductor devices with control electrode {, e.g. charge pumps}
- H02M: APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF (transformers H01F; dynamo-electric converters H02K47/00; controlling transformers, reactors or choke coils, control or regulation of electric motors, generators or dynamo-electric converters H02P)

## Abstract

An electronic device includes: a clock booster including a doubler capacitor, the clock booster configured to precharge the doubler capacitor and provide a boosted intermediate voltage greater than an input voltage; a secondary booster including a booster capacitor, the secondary booster configured to use the voltage stored on the doubler capacitor to generate a stage output greater than the boosted intermediate voltage; and a connecting switch connected to the clock booster and the secondary booster, the connecting switch configured to electrically connect the doubler capacitor and the booster capacitor during a direct charging duration for charging the booster capacitor using source-secondary current from an input voltage supply instead of or in addition to the voltage stored on the doubler capacitor.

## Claims

### Claim 1

An electronic device, comprising:
a clock booster including:
a slave booster that includes a doubler capacitor, the slave booster configured to provide charges for a connected circuit, and
a master-controller directly connected to the slave booster, the master-controller configured to control a switch that controls charging of the doubler capacitor,
the clock booster configured to precharge the doubler capacitor and provide a boosted intermediate voltage greater than an input voltage;
a secondary booster including a booster capacitor, the secondary booster configured to use the voltage stored on the doubler capacitor in the slave booster to generate a stage output greater than the boosted intermediate voltage;
a connecting switch connected to the clock booster and the secondary booster, the connecting switch configured to electrically connect the doubler capacitor and the booster capacitor during a direct charging duration for charging the booster capacitor using source-secondary current from an input voltage supply instead of or in addition to the voltage stored on the doubler capacitor; and
a control circuitry configured to:
control a clock signal that is connected to the doubler capacitor opposite the connecting switch, and configured to charge the doubler capacitor, wherein the clock signal is at a low state during the direct charging duration,
control a clock master signal that is connected to a controller capacitor in the master-controller and connected opposite the input voltage, configured to charge the controller capacitor for controlling the slave booster, wherein the clock master signal is at a high state during the direct charging duration,
control a module signal during the direct charging duration for closing the connecting switch, and
reverting the module signal module signal to a prior state after the direct charging duration;
wherein:
the connecting switch is configured to remain closed after the direct charging duration based on voltage levels at an input and output of the connecting switch instead of the module signal.

### Claim 2 (depends on 1)

The electronic device of claim 1, further comprising a discharging switch connected to the secondary booster, configured to discharge from the booster capacitor charges remaining after a recycling duration.

### Claim 3 (depends on 2)

The electronic device of claim 2, wherein the connecting switch and the discharging switch are for replacing one or more inverters between the clock doubler and the secondary booster.

### Claim 4 (depends on 3)

The electronic device of claim 3, wherein the connecting switch and the discharging switch are complementary to each other.

### Claim 5 (depends on 4)

The electronic device of claim 4, wherein the connecting switch and the discharging switch include a PMOS transistor and an NMOS transistor.

### Claim 6 (depends on 1)

The electronic device of claim 1, wherein the secondary booster is a Favrat booster.

### Claim 7

A method of operating an electronic device, comprising:
closing a connecting switch at a beginning of a direct charging duration, wherein:
the connecting switch is configured to connect a clock doubler to a secondary booster,
the secondary booster is configured to generate a stage output voltage, and closing the connecting switch includes:
closing the connecting switch after discharging charges stored in the secondary booster through a discharging switch, and
controlling a voltage at a control node of the connecting switch with a module signal;
opening the discharging switch before the direct charging duration for isolating a booster capacitor in the secondary booster from a node with voltage level lower than the booster capacitor;
closing a source switch at the beginning of the direct charging duration for directly charging the secondary booster using an input voltage;
keeping a clock signal at a low state during the direct charging duration, wherein:
the clock signal is configured to charge a doubler capacitor within a clock doubler, and
the doubler capacitor is connected to the input voltage through the source switch;
keeping the connecting switch closed after the direct charging duration based on voltages at input and output terminals of the connecting switch for further charging the secondary booster using the doubler capacitor; and
reverting voltage at the control node after the direct charging duration to a previous state.

### Claim 8 (depends on 7)

The method of claim 7, wherein:
the clock signal is configured to charge the doubler capacitor included in a slave-booster of the clock doubler; and further comprising:
maintaining a clock master signal during the direct charging duration, wherein the clock master signal is configured to operate a master-controller that is configured to control the slave-booster without directly contributing to charging the doubler capacitor.

### Claim 9 (depends on 8)

The method of claim 8, wherein maintaining the clock master signal includes maintaining the clock master signal at a state for closing the source switch when the clock signal is at the low state.

### Claim 10 (depends on 9)

The method of claim 9, further comprising driving the clock master signal to the low state after the direct charging duration for operating the source switch including an NMOS device.

### Claim 11 (depends on 7)

The method of claim 7, further comprising:
driving the clock signal to a high state after the direct charging duration for boosting electrical potential of the doubler capacitor; and
charging the secondary booster based on the doubler capacitor.

### Claim 12 (depends on 7)

The method of claim 7, further comprising maintaining the voltage at the control node after the direct charging duration for keeping the connecting switch closed.