# US 10,312,438 B1 · Resistive memory with amorphous silicon filaments

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- Number: US 10,312,438 B1
- Document ID: US10312438B1
- Status: Granted
- Kind: B1
- Application number: 15/845,830
- Filed: 2017-12-18
- Published: 2019-06-20
- Granted: 2019-06-04
- Earliest claimed: 2017-12-18
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: Alexander Reznicek; Bahman Hekmatshoartabari
- Web page: https://patentgrep.com/patent/US10312438B1

## CPC

- H10N 70/245: {the species being metal cations, e.g. programmable metallization cells}
- H10B 63/80: {Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays}
- H10N 70/023: {by chemical vapor deposition, e.g. MOCVD, ALD}
- H10N 70/041: {Modification of switching materials after formation, e.g. doping (shaping H10N70/061)}
- H10N 70/063: {by etching of pre-deposited switching material layers, e.g. lithography}
- H10N 70/826: {adapted for essentially vertical current flow, e.g. sandwich or pillar type devices}
- H10N 70/8416: {adapted for supplying ionic species}
- H10N 70/884: {based on at least one element of group IIIA, IVA or VA, e.g. elemental or compound semiconductors (compounds of sulfur, selenium or tellurium, e.g. chalcogenides H10N70/882; oxides or nitrides H10N70/883)}
- H10W 20/43: Layouts of interconnections
- H10B 63/20: {comprising selection components having two electrodes, e.g. diodes}
- H10N: ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B: ELECTRONIC MEMORY DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A method for manufacturing a semiconductor memory device includes forming a first silicon layer on a bottom conductive layer, transforming the first silicon layer into a first polysilicon layer, forming a second silicon layer stacked on the first polysilicon layer, and a third silicon layer stacked on the second silicon layer, transforming the second and third silicon layers into second and third polysilicon layers, wherein the first and third polysilicon layers have a first doping type, and the second polysilicon layer has a second doping type different from the first doping type, forming an amorphous silicon layer on the third polysilicon layer, and forming a top conductive layer on the amorphous silicon layer.

## Claims

### Claim 1

A method for manufacturing a semiconductor memory device, comprising:
forming a first silicon layer on a bottom conductive layer;
transforming the first silicon layer into a first polysilicon layer;
forming a second silicon layer stacked on the first polysilicon layer, and a third silicon layer stacked on the second silicon layer;
transforming the second and third silicon layers into second and third polysilicon layers;
wherein the first and third polysilicon layers have a first doping type, and the second polysilicon layer has a second doping type different from the first doping type;
forming an amorphous silicon layer on the third polysilicon layer; and
forming a top conductive layer on the amorphous silicon layer.

### Claim 2 (depends on 1)

The method according to claim 1, wherein the transforming of the first, second and third silicon layers is performed at a temperature less than 400° C.

### Claim 3 (depends on 1)

The method according to claim 1, wherein the transforming of the first, second and third silicon layers is performed using a laser annealing process.

### Claim 4 (depends on 1)

The method according to claim 1, wherein the first, second and third silicon layers comprise at least one of amorphous silicon, nano-crystalline silicon and micro-crystalline silicon.

### Claim 5 (depends on 1)

The method according to claim 1, further comprising planarizing the first polysilicon layer in order to remove one or more surface protrusions formed on the first polysilicon layer as a result of the transforming of the first silicon layer.

### Claim 6 (depends on 1)

The method according to claim 1, wherein forming the second and third silicon layers comprises epitaxially growing the second and third silicon layers.

### Claim 7 (depends on 1)

The method according to claim 1, further comprising patterning a stacked structure of the amorphous silicon layer on the first, second and third polysilicon layers into a plurality of stacked structures spaced apart from each other on the bottom conductive layer.

### Claim 8 (depends on 7)

The method according to claim 7, further comprising depositing a dielectric layer on the bottom conductive layer between the plurality of stacked structures.

### Claim 9 (depends on 1)

The method according to claim 1, further comprising:
patterning the bottom conductive layer into a plurality of wordlines;
patterning the top conductive layer into a plurality of bitlines;
wherein the plurality of bitlines are oriented perpendicularly with respect to the plurality of wordlines.

### Claim 10 (depends on 1)

The method according to claim 1, further comprising patterning a stacked structure of the amorphous silicon layer and the first, second and third polysilicon layers on the bottom conductive layer into a plurality of stacked structures spaced apart from each other.

### Claim 11 (depends on 10)

The method according to claim 10, further comprising depositing a dielectric layer between the plurality of stacked structures.

### Claim 12 (depends on 11)

The method according to claim 11, further comprising patterning the top conductive layer into a plurality of bitlines, wherein the plurality of bitlines cover first portions of the plurality of stacked structures, and remaining portions of the plurality of stacked structures not covered by the plurality of bitlines are exposed.

### Claim 13 (depends on 12)

The method according to claim 12, further comprising removing the remaining portions of the plurality of stacked structures down to the bottom conductive layer.

### Claim 14 (depends on 13)

The method according to claim 13, further comprising depositing another dielectric layer in spaces left by the removal of the remaining portions of the plurality of stacked structures.

### Claim 15

A method for manufacturing a semiconductor memory device, comprising:
forming a first silicon layer on a bottom conductive layer;
crystallizing the first silicon layer;
forming a second silicon layer stacked on the crystallized first silicon layer, and a third silicon layer stacked on the second silicon layer;
crystallizing the second and third silicon layers;
wherein the crystallized first and third silicon layers have a first doping type, and the crystallized second silicon layer has a second doping type different from the first doping type;
forming an amorphous silicon layer on the crystallized third silicon layer; and
forming a top conductive layer on the amorphous silicon layer.

### Claim 16 (depends on 15)

The method according to claim 15, wherein the crystallizing of the first, second and third silicon layers is performed at a temperature less than 400° C.