# US 10,312,401 B2 · Method for producing an optoelectronic semiconductor chip and optoelectronic semiconductor chip

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- Number: US 10,312,401 B2
- Document ID: US10312401B2
- Status: Granted
- Kind: B2
- Application number: 15/115,242
- Filed: 2015-02-13
- Published: 2017-01-05
- Granted: 2019-06-04
- Earliest claimed: 2014-02-17
- Assignees: OSRAM Opto Semiconductors GmbH
- Applicants: OSRAM Opto Semiconductors GmbH
- Inventors: Werner Bergbauer; Thomas Lehnhardt; Jürgen Off; Joachim Hertkorn
- Web page: https://patentgrep.com/patent/US10312401B2

## CPC

- H10F 71/1276: {comprising growth substrates not made of Group III-V materials}
- H10F 71/1278: {comprising nitrides, e.g. GaN}
- H10F 77/1246: {III-V nitrides, e.g. GaN}
- H10H 20/0133: {with a substrate not being Group III-V materials}
- H10H 20/01335: {the light-emitting regions comprising nitride materials}
- H10H 20/0137: {the light-emitting regions comprising nitride materials}
- H10H 20/815: having stress relaxation structures, e.g. buffer layers
- H10H 20/82: Roughened surfaces, e.g. at the interface between epitaxial layers
- H10H 20/825: containing nitrogen, e.g. GaN
- H10P 14/271: {characterised by the preparation of substrate for selective deposition}
- H10P 14/276: {Lateral overgrowth}
- H10P 14/2925: {Surface structures}
- H10P 14/3216: {Nitrides}
- H10P 14/3416: {Nitrides}
- H10H 20/036: {of packages}
- H10P 14/3238: {being insulating materials}
- H10F: INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
- H10H: INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A method for producing an electronic semiconductor chip and a semiconductor chip are disclosed. In embodiments, the method includes providing a growth substrate having a growth surface formed by a flat region having a plurality of three-dimensional surface structures on the flat region, directly applying a nucleation layer of oxygen-containing AlN over a large area to the growth surface and growing a nitride-based semiconductor layer sequence on the nucleation layer, wherein growing the semiconductor layer sequence includes selectively growing the semiconductor layer sequence upwards from the flat region.

## Claims

### Claim 1

A method for producing an electronic semiconductor chip, the method comprising:
providing a growth substrate comprising a growth surface formed by a planar region having a plurality of three-dimensional surface structures on the planar region;
directly applying a nucleation layer of oxygen-containing AlN over a large area to the growth surface;
growing a nitride-based semiconductor layer sequence on the nucleation layer, wherein growing the semiconductor layer sequence comprises selectively growing the semiconductor layer sequence upwards from the planar region such that a growth of the semiconductor layer sequence on the whole surfaces of the three-dimensional surface structures is reduced or non-existent compared to a growth on the planar region; and
directly applying a nucleation layer of oxygen-containing AlN in such a way that the entire growth surface, the entire planar region and the surface structures are covered by the nucleation layer, wherein an oxygen content of the nucleation layer is more than 1019 cm−3, and wherein a selectivity of the growth of the semiconductor layer sequence on the planar region is targetedly adjusted by the oxygen content of the nucleation layer.

### Claim 2 (depends on 1)

The method according to claim 1, wherein the three-dimensional surface structures are substantially covered by the semiconductor layer sequence while growing the semiconductor layer sequence.

### Claim 3 (depends on 1)

The method according to claim 1, wherein applying the nucleation layer is ensued by a metal-organic vapor-phase epitaxy.

### Claim 4 (depends on 1)

The method according to claim 1, wherein applying the nucleation layer is ensued by sputtering.

### Claim 5 (depends on 1)

The method according to claim 1, wherein the three-dimensional surface structures comprise conical or pyramidal elevations on the planar region.

### Claim 6 (depends on 1)

The method according to claim 1, wherein the growth substrate comprises aluminum oxide.

### Claim 7 (depends on 6)

The method according to claim 6, wherein the planar region is a crystallographic c surface.

### Claim 8 (depends on 1)

The method according to claim 1, wherein the semiconductor layer sequence is grown with an optoelectronic active layer, which is provided for emitting or detecting light during operation of the semiconductor chip.

### Claim 9 (depends on 8)

The method according to claim 8, wherein the semiconductor chip is designed as a light-emitting or light-detecting diode.

### Claim 10

An electronic semiconductor chip comprising:
a growth substrate with a growth surface, which is formed by a planar region having a plurality of three-dimensional surface structures on the planar region;
a nucleation layer composed of oxygen-containing AlN directly disposed on the growth surface;
a nitride-based semiconductor layer sequence disposed on the nucleation layer, wherein the semiconductor layer sequence is selectively grown from the planar region such that a growth of the semiconductor layer sequence on the whole surfaces of the three-dimensional surface structures is reduced or non-existent compared to a growth on the planar region; and
a nucleation layer of oxygen-containing AlN is directly applied in such a way that the entire growth surface, the entire planar region and the surface structures are covered by the nucleation layer, wherein an oxygen content of the nucleation layer is more than 1019 cm−3, and wherein a selectivity of the growth of the semiconductor layer sequence on the planar region is targetedly adjusted by the oxygen content of the nucleation layer.

### Claim 11 (depends on 1)

The method according to claim 1, wherein the nucleation layer is applied to the growth surface with a thickness of greater than or equal to 1 nm, and wherein the nucleation layer is applied by sputtering or MOVPE.

### Claim 12 (depends on 1)

The method according to claim 1, wherein the nucleation layer is applied to the growth surface with a thickness of greater than or equal to 5 nm.

### Claim 13 (depends on 1)

The method according to claim 1, wherein a weight proportion of oxygen in the nucleation layer is greater than or equal to 0.1%.

### Claim 14

A method for producing an electronic semiconductor chip, the method comprising:
providing a growth substrate comprising a growth surface formed by a planar region having a plurality of three-dimensional surface structures on the planar region;
directly applying a nucleation layer of oxygen-containing AlN over a large area to the growth surface;
growing a nitride-based semiconductor layer sequence on the nucleation layer, wherein growing the semiconductor layer sequence comprises selectively growing the semiconductor layer sequence upwards from the planar region such that a growth of the semiconductor layer sequence on the whole surfaces of the three-dimensional surface structures is reduced or non-existent compared to a growth on the planar region; and
directly applying a nucleation layer of oxygen-containing AlN in such a way that the entire growth surface, the entire planar region and the surface structures are covered by the nucleation layer, wherein an oxygen content of the nucleation layer is more than 1019 cm−3, and wherein the oxygen content of the nucleation layer is adjusted in such a way that the semiconductor layer sequence is predominantly grown from the planar region, whereas very little or no growth at all of the semiconductor layer sequence takes place on the three-dimensional surface structures.