# US 10,312,381 B2 · III-V semiconductor diode > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,312,381 B2 - Document ID: US10312381B2 - Status: Granted - Kind: B2 - Application number: 15/936,330 - Filed: 2018-03-26 - Published: 2018-09-27 - Granted: 2019-06-04 - Earliest claimed: 2017-03-24 - Assignees: 3-5 Power Electronics GmbH - Applicants: 3-5 Power Electronics GmbH - Inventors: Volker Dudek - Web page: https://patentgrep.com/patent/US10312381B2 ## CPC - H10D 8/60: Schottky-barrier diodes - H10D 8/00: Diodes (variable-capacitance diodes H10D1/64; gated diodes H10D12/00) - H10D 62/53: the imperfections being within the semiconductor body - H10D 62/60: Impurity distributions or concentrations - H10D 62/85: being Group III-V materials, e.g. GaAs - H10D 8/043: {of planar diodes} - H10D 8/051: {of Schottky diodes} - H10P 10/128: {by direct semiconductor to semiconductor bonding} - H10P 14/3421: {Arsenides} - H10P 30/206: {into Group III-V semiconductors} - H10P 30/21: {of electrically active species} - H10P 52/402: {of semiconductor materials} - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 ## Abstract A stacked III-V semiconductor diode that has an n+ layer having a dopant concentration of at least 1019 N/cm3, an n− layer having a dopant concentration of 1012 N/cm3 to 1016 N/cm3, a layer thickness of 10 μm to 300 μm, a p+ layer having a dopant concentration of 5·1018 N/cm3 to 5·1020 cm3 and a layer thickness greater than 2 μm, the layers following each other in the specified order, each including a GaAs compound or being made from a GaAs compound and having a monolithic design, the n+ layer or the p+ layer being a substrate, and a lower side of the n− layer being integrally connected to an upper side of the n+ layer. The stacked III-V semiconductor diode including a first defect layer having a layer thickness greater than 0.5 μm, the defect layer being situated within the n− layer. ## Claims ### Claim 1 A stacked III-V semiconductor diode comprising: an n+ layer having an upper side, a lower side, a dopant concentration of at least 1019 N/cm3 and a layer thickness between 50 μm and 400 μm, the n+ layer comprising a GaAs compound; an n− layer having an upper side, and a lower side, a dopant concentration of 1012 N/cm3 to 1016 N/cm3, a layer thickness of 10 μm to 300 μm, the n− layer comprising a GaAs compound; a p+ layer having an upper side, a lower side, a dopant concentration of 5·1018 N/cm3 to 5·1020 N/cm3, a layer thickness of at least 2 μm, the p+ layer comprising a GaAs compound; and a first defect layer having a layer thickness between 0.5 μm and 50 μm, the defect layer being arranged within the n− layer, the defect layer having a defect concentration in a range between 1·1013 N/cm3 and 5·1016 N/cm3, wherein the n+-layer, the n−-layer, and the p+-layer are monolithically formed, wherein the n+ layer or the p+ layer is formed as a substrate, and wherein the lower side of the n− layer is integrally connected to the upper side of the n+ layer. ### Claim 2 (depends on 1) The III-V semiconductor diode according to claim 1, wherein the first defect layer has a distance from the lower side of the n″ layer of at least half the layer thickness of the n″ layer. ### Claim 3 (depends on 1) The III-V semiconductor diode according to claim 1, wherein the semiconductor diode includes a second defect layer, the second defect layer having a layer thickness between 0.5 μm and 50 μm and a defect concentration between 1·1013 N/cm3 and 5·1016 N/cm3 and a distance from the upper side of the n″ layer of no more than half the layer thickness of the n− layer. ### Claim 4 (depends on 1) The III-V semiconductor diode according to claim 1, wherein the first defect layer and/or a second defect layer each have a first layer area with a first detect concentration and a second layer area with a second defect concentration. ### Claim 5 (depends on 1) The III-V semiconductor diode according to claim 1, wherein the defect concentration over the layer thickness of the first defect layer and/or a layer thickness of a second defect layer follow a statistical distribution. ### Claim 6 (depends on 1) The III-V semiconductor diode according to claim 1, wherein the first defect layer and/or a second defect layer include Cr and/or indium and/or aluminum. ### Claim 7 (depends on 1) The III-V semiconductor diode according to claim 1, wherein the III-V semiconductor diode includes an n-doped or p-doped intermediate layer having a layer thickness of 1 μm to 50 μm and a dopant concentration of 1012 N/cm3 to 1017 N/cm3, the intermediate layer being integrally connected to the p+ layer and to the n− layer. ### Claim 8 (depends on 1) The III-V semiconductor diode according to claim 1, wherein a total height of a stacked layer structure comprising the p+ layer, the n− layer, and the n+ layer, is no more than 150 μm to 800 μm. ### Claim 9 (depends on 1) The III-V semiconductor diode according to claim 1, wherein a stacked layer structure comprising the p+ layer, the n− layer, and the n+ layer has a rectangular or square surface with edge lengths between 1 mm and 10 mm. ### Claim 10 (depends on 1) The III-V semiconductor diode according to claim 1, wherein a stacked layer structure comprising the p+ layer, the n− layer, and the n+ layer has a round or oval or circular surface. ### Claim 11 (depends on 1) The III-V semiconductor diode according to claim 1, wherein the III-V semiconductor diode has a monolithic design or includes a semiconductor bond. ### Claim 12 (depends on 11) The III-V semiconductor diode according to claim 11, wherein the semiconductor bond is formed between the p+ layer and the n− layer or between a p− layer and the n− layer. ### Claim 13 (depends on 1) The III-V semiconductor diode according to claim 1, wherein the n+ layer, the n− layer, or the p+ layer consists essentially of the GaAs compound. ### Claim 14 A stacked III-V semiconductor diode comprising: an n+ layer having an upper side, a lower side, a dopant concentration of at least 1019 N/cm3 and a layer thickness between 50 μm and 400 μm, the n+ layer comprising a GaAs compound; an n− layer having an upper side, and a lower side, a dopant concentration of 1012N/cm3 to 1016 N/cm3, a layer thickness of 10 μm to 300 μm, the n− layer comprising a GaAs compound; a terminal contact layer; and a first defect layer having a layer thickness between 0.5 μm and 50 μm, the defect layer being arranged within the n− layer, the defect layer having a defect concentration in a range between 1·1013 N/cm3 and 5·1016 N/cm3, wherein the n+-layer, the n−-layer, and the p+-layer are monolithically formed, wherein the n+ layer or the terminal contact layer is formed as a substrate, and wherein the lower side of the n− layer is integrally connected to the upper side of the n+ layer, wherein the terminal contact layer includes a metal or a metallic compound or is made from the metal or the metallic compound and forms a Schottky contact.